From fb940b6e9622055706ff000a4d1033939f4d4dca Mon Sep 17 00:00:00 2001 From: Suzuki K Poulose Date: Tue, 8 Nov 2022 14:37:59 +0800 Subject: [PATCH] arm64: Add support for trace synchronization barrier mainline inclusion from mainline-v5.12-rc3 commit be96826942e8 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK CVE: NA Reference: https://lore.kernel.org/r/20210405164307.1720226-4-suzuki.poulose@arm.com -------------------------------------------------------------------------- tsb csync synchronizes the trace operation of instructions. The instruction is a nop when FEAT_TRF is not implemented. Cc: Mathieu Poirier Cc: Mike Leach Cc: Catalin Marinas Cc: Will Deacon Acked-by: Catalin Marinas Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20210405164307.1720226-4-suzuki.poulose@arm.com Signed-off-by: Mathieu Poirier --- arch/arm64/include/asm/barrier.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 2a13b1c2c390..f150a862dadd 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -23,6 +23,7 @@ #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define psb_csync() asm volatile("hint #17" : : : "memory") +#define tsb_csync() asm volatile("hint #18" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory") /* -- GitLab