diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index 228a657e4fa8ba575fefae5ab2cdae177e3b6b92..9539dd93c4a76b81a821d26fa895155db2c8388d 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -3524,6 +3524,7 @@ CONFIG_HW_RANDOM_INTEL=m CONFIG_HW_RANDOM_AMD=m # CONFIG_HW_RANDOM_BA431 is not set CONFIG_HW_RANDOM_VIA=m +CONFIG_HW_RANDOM_ZHAOXIN=m CONFIG_HW_RANDOM_VIRTIO=y # CONFIG_HW_RANDOM_XIPHERA is not set # CONFIG_APPLICOM is not set diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 87cebb34aeccdad84d581343250dd4ea57cc2e57..53e63d68ffb1b838b8bf4d7c42a709d558e9d4b9 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -137,6 +137,20 @@ config HW_RANDOM_N2RNG If unsure, say Y. + +config HW_RANDOM_ZHAOXIN + tristate "Zhaoxin HW Random Number Generator support" + depends on X86 + default HW_RANDOM + help + This driver provides kernel-side support for the Random Number + Generator hardware found on Zhaoxin based motherboards. + + To compile this driver as a module, choose M here: the + module will be called zhaoxin-rng. + + If unsure, say Y. + config HW_RANDOM_VIA tristate "VIA HW Random Number Generator support" depends on X86 diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index d24ec71627af3182973212b5b78f5a1b10c22457..67377d9e10f7d09dfb7783c9900a55956af05242 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o n2-rng-y := n2-drv.o n2-asm.o obj-$(CONFIG_HW_RANDOM_VIA) += via-rng.o +obj-$(CONFIG_HW_RANDOM_ZHAOXIN) += zhaoxin-rng.o obj-$(CONFIG_HW_RANDOM_EXYNOS) += exynos-trng.o obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c index 39943bc3651a61e10a634dbbbc3e5ee980e2506a..fe1c1e493be423a100062903aaa1c828154e11ef 100644 --- a/drivers/char/hw_random/via-rng.c +++ b/drivers/char/hw_random/via-rng.c @@ -191,12 +191,17 @@ static struct hwrng via_rng = { .data_read = via_rng_data_read, }; +static struct x86_cpu_id via_rng_ids[] = { + { X86_VENDOR_CENTAUR, 6, X86_MODEL_ANY, X86_FEATURE_XSTORE }, + {} +}; +MODULE_DEVICE_TABLE(x86cpu, via_rng_ids); static int __init mod_init(void) { int err; - if (!boot_cpu_has(X86_FEATURE_XSTORE)) + if (!x86_match_cpu(via_rng_ids)) return -ENODEV; pr_info("VIA RNG detected\n"); diff --git a/drivers/char/hw_random/zhaoxin-rng.c b/drivers/char/hw_random/zhaoxin-rng.c new file mode 100644 index 0000000000000000000000000000000000000000..f73b6cb524db7fac1d436337c5d1e7d811a26a8d --- /dev/null +++ b/drivers/char/hw_random/zhaoxin-rng.c @@ -0,0 +1,170 @@ +/* + * RNG driver for Zhaoxin RNGs + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + + + +enum { + ZHAOXIN_STRFILT_CNT_SHIFT = 16, + ZHAOXIN_STRFILT_FAIL = (1 << 15), + ZHAOXIN_STRFILT_ENABLE = (1 << 14), + ZHAOXIN_RAWBITS_ENABLE = (1 << 13), + ZHAOXIN_RNG_ENABLE = (1 << 6), + ZHAOXIN_NOISESRC1 = (1 << 8), + ZHAOXIN_NOISESRC2 = (1 << 9), + ZHAOXIN_XSTORE_CNT_MASK = 0x0F, + + ZHAOXIN_RNG_CHUNK_8 = 0x00, /* 64 rand bits, 64 stored bits */ + ZHAOXIN_RNG_CHUNK_4 = 0x01, /* 32 rand bits, 32 stored bits */ + ZHAOXIN_RNG_CHUNK_4_MASK = 0xFFFFFFFF, + ZHAOXIN_RNG_CHUNK_2 = 0x02, /* 16 rand bits, 32 stored bits */ + ZHAOXIN_RNG_CHUNK_2_MASK = 0xFFFF, + ZHAOXIN_RNG_CHUNK_1 = 0x03, /* 8 rand bits, 32 stored bits */ + ZHAOXIN_RNG_CHUNK_1_MASK = 0xFF, +}; + +/* + * Investigate using the 'rep' prefix to obtain 32 bits of random data + * in one insn. The upside is potentially better performance. The + * downside is that the instruction becomes no longer atomic. Due to + * this, just like familiar issues with /dev/random itself, the worst + * case of a 'rep xstore' could potentially pause a cpu for an + * unreasonably long time. In practice, this condition would likely + * only occur when the hardware is failing. (or so we hope :)) + * + * Another possible performance boost may come from simply buffering + * until we have 4 bytes, thus returning a u32 at a time, + * instead of the current u8-at-a-time. + * + * Padlock instructions can generate a spurious DNA fault, but the + * kernel doesn't use CR0.TS, so this doesn't matter. + */ + +static inline u32 xstore(u32 *addr, u32 edx_in) +{ + u32 eax_out; + + asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */" + : "=m" (*addr), "=a" (eax_out), "+d" (edx_in), "+D" (addr)); + + return eax_out; +} + +static int zhaoxin_rng_data_present(struct hwrng *rng, int wait) +{ + char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__ + ((aligned(STACK_ALIGN))); + u32 *zhaoxin_rng_datum = (u32 *)PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT); + u32 bytes_out; + int i; + + /* We choose the recommended 1-byte-per-instruction RNG rate, + * for greater randomness at the expense of speed. Larger + * values 2, 4, or 8 bytes-per-instruction yield greater + * speed at lesser randomness. + * + * If you change this to another ZHAOXIN_CHUNK_n, you must also + * change the ->n_bytes values in rng_vendor_ops[] tables. + * ZHAOXIN_CHUNK_8 requires further code changes. + * + * A copy of MSR_ZHAOXIN_RNG is placed in eax_out when xstore + * completes. + */ + + for (i = 0; i < 20; i++) { + *zhaoxin_rng_datum = 0; /* paranoia, not really necessary */ + bytes_out = xstore(zhaoxin_rng_datum, ZHAOXIN_RNG_CHUNK_1); + bytes_out &= ZHAOXIN_XSTORE_CNT_MASK; + if (bytes_out || !wait) + break; + udelay(10); + } + rng->priv = *zhaoxin_rng_datum; + return bytes_out ? 1 : 0; +} + +static int zhaoxin_rng_data_read(struct hwrng *rng, u32 *data) +{ + u32 zhaoxin_rng_datum = (u32)rng->priv; + + *data = zhaoxin_rng_datum; + + return 1; +} + +static int zhaoxin_rng_init(struct hwrng *rng) +{ + struct cpuinfo_x86 *c = &cpu_data(0); + + /* Zhaoxin CPUs don't have the MSR_ZHAOXIN_RNG anymore. The RNG + * is always enabled if CPUID rng_en is set. There is no + * RNG configuration like it used to be the case in this + * register */ + if (c->x86 > 6) { + if (!boot_cpu_has(X86_FEATURE_XSTORE_EN)) { + pr_err(PFX "can't enable hardware RNG " + "if XSTORE is not enabled\n"); + return -ENODEV; + } + return 0; + } + return 0; +} + + +static struct hwrng zhaoxin_rng = { + .name = "zhaoxin", + .init = zhaoxin_rng_init, + .data_present = zhaoxin_rng_data_present, + .data_read = zhaoxin_rng_data_read, +}; + +static struct x86_cpu_id zhaoxin_rng_ids[] = { + { X86_VENDOR_CENTAUR, 7, X86_MODEL_ANY, X86_STEPPING_ANY, X86_FEATURE_XSTORE }, + { X86_VENDOR_ZHAOXIN, 7, X86_MODEL_ANY, X86_STEPPING_ANY, X86_FEATURE_XSTORE }, + {} +}; +MODULE_DEVICE_TABLE(x86cpu, zhaoxin_rng_ids); + +static int __init mod_init(void) +{ + int err; + + if (!x86_match_cpu(zhaoxin_rng_ids)) + return -ENODEV; + + pr_info("RNG detected\n"); + err = hwrng_register(&zhaoxin_rng); + if (err) + pr_err(PFX "RNG registering failed (%d)\n", err); + + return err; +} +module_init(mod_init); + +static void __exit mod_exit(void) +{ + hwrng_unregister(&zhaoxin_rng); +} +module_exit(mod_exit); + +static struct x86_cpu_id __maybe_unused zhaoxin_rng_cpu_id[] = { + X86_MATCH_FEATURE(X86_FEATURE_XSTORE, NULL), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, zhaoxin_rng_cpu_id); + +MODULE_DESCRIPTION("H/W RNG driver for Zhaoxin CPU with PadLock"); +MODULE_LICENSE("GPL");