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提交 ec5ebd2c 编写于 作者: S Sreekanth Reddy 提交者： Martin K. Petersen
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scsi: mpi3mr: Update MPI3 headers - part2 

Continued updating MPI3 headers.

Link: https://lore.kernel.org/r/20211220141159.16117-6-sreekanth.reddy@broadcom.comSigned-off-by: NSreekanth Reddy <sreekanth.reddy@broadcom.com>
Signed-off-by: NMartin K. Petersen <martin.petersen@oracle.com>
上级 d00ff7c3
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Showing with 261 addition and 61 deletion
drivers/scsi/mpi3mr/mpi/mpi30_image.h
浏览文件 @ ec5ebd2c
...@@ -61,6 +61,8 @@ struct mpi3_component_image_header { ...@@ -61,6 +61,8 @@ struct mpi3_component_image_header {
#define MPI3_IMAGE_HEADER_SIGNATURE1_SPD (0x20445053) #define MPI3_IMAGE_HEADER_SIGNATURE1_SPD (0x20445053)
#define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE (0x20534147) #define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE (0x20534147)
#define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP (0x504c4250) #define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP (0x504c4250)
#define MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST (0x464e414d)
#define MPI3_IMAGE_HEADER_SIGNATURE1_OEM (0x204d454f)
#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546) #define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030) #define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030)
#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000) #define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000)
...@@ -94,6 +96,61 @@ struct mpi3_component_image_header { ...@@ -94,6 +96,61 @@ struct mpi3_component_image_header {
#define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET (0x5c) #define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET (0x5c)
#define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET (0x7c) #define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET (0x7c)
#define MPI3_IMAGE_HEADER_SIZE (0x100) #define MPI3_IMAGE_HEADER_SIZE (0x100)
#ifndef MPI3_CI_MANIFEST_MPI_MAX
#define MPI3_CI_MANIFEST_MPI_MAX (1)
#endif
struct mpi3_ci_manifest_mpi_comp_image_ref {
__le32 signature1;
__le32 reserved04[3];
struct mpi3_comp_image_version component_image_version;
__le32 component_image_version_string_offset;
__le32 crc;
};
struct mpi3_ci_manifest_mpi {
u8 manifest_type;
u8 reserved01[3];
__le32 reserved04[3];
u8 num_image_references;
u8 release_level;
__le16 reserved12;
__le16 reserved14;
__le16 flags;
__le32 reserved18[2];
__le16 vendor_id;
__le16 device_id;
__le16 subsystem_vendor_id;
__le16 subsystem_id;
__le32 reserved28[2];
union mpi3_version_union package_security_version;
__le32 reserved34;
struct mpi3_comp_image_version package_version;
__le32 package_version_string_offset;
__le32 package_build_date_string_offset;
__le32 package_build_time_string_offset;
__le32 reserved4c;
__le32 diag_authorization_identifier[16];
struct mpi3_ci_manifest_mpi_comp_image_ref component_image_ref[MPI3_CI_MANIFEST_MPI_MAX];
};
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_DEV (0x00)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_PREALPHA (0x10)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_ALPHA (0x20)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_BETA (0x30)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_RC (0x40)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_GCA (0x50)
#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_POINT (0x60)
#define MPI3_CI_MANIFEST_MPI_FLAGS_DIAG_AUTHORIZATION (0x01)
#define MPI3_CI_MANIFEST_MPI_SUBSYSTEMID_IGNORED (0xffff)
#define MPI3_CI_MANIFEST_MPI_PKG_VER_STR_OFF_UNSPECIFIED (0x00000000)
#define MPI3_CI_MANIFEST_MPI_PKG_BUILD_DATE_STR_OFF_UNSPECIFIED (0x00000000)
#define MPI3_CI_MANIFEST_MPI_PKG_BUILD_TIME_STR_OFF_UNSPECIFIED (0x00000000)
union mpi3_ci_manifest {
struct mpi3_ci_manifest_mpi mpi;
__le32 dword[1];
};
#define MPI3_CI_MANIFEST_TYPE_MPI (0x00)
struct mpi3_extended_image_header { struct mpi3_extended_image_header {
u8 image_type; u8 image_type;
u8 reserved01[3]; u8 reserved01[3];
...@@ -161,6 +218,7 @@ struct mpi3_encrypted_hash_entry { ...@@ -161,6 +218,7 @@ struct mpi3_encrypted_hash_entry {
#define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00) #define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00)
#define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01) #define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01)
#define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02) #define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02)
#define MPI3_HASH_ALGORITHM_SIZE_SHA384 (0x03)
#define MPI3_ENCRYPTION_ALGORITHM_UNUSED (0x00) #define MPI3_ENCRYPTION_ALGORITHM_UNUSED (0x00)
#define MPI3_ENCRYPTION_ALGORITHM_RSA256 (0x01) #define MPI3_ENCRYPTION_ALGORITHM_RSA256 (0x01)
#define MPI3_ENCRYPTION_ALGORITHM_RSA512 (0x02) #define MPI3_ENCRYPTION_ALGORITHM_RSA512 (0x02)
...@@ -178,7 +236,6 @@ struct mpi3_encrypted_key_with_hash_entry { ...@@ -178,7 +236,6 @@ struct mpi3_encrypted_key_with_hash_entry {
u8 reserved03; u8 reserved03;
__le32 reserved04; __le32 reserved04;
__le32 public_key[MPI3_PUBLIC_KEY_MAX]; __le32 public_key[MPI3_PUBLIC_KEY_MAX];
__le32 encrypted_hash[MPI3_ENCRYPTED_HASH_MAX];
}; };
#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX #ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX
......
drivers/scsi/mpi3mr/mpi/mpi30_init.h
浏览文件 @ ec5ebd2c
...@@ -13,7 +13,7 @@ struct mpi3_scsi_io_cdb_eedp32 { ...@@ -13,7 +13,7 @@ struct mpi3_scsi_io_cdb_eedp32 {
__le32 transfer_length; __le32 transfer_length;
}; };
union mpi3_scso_io_cdb_union { union mpi3_scsi_io_cdb_union {
u8 cdb32[32]; u8 cdb32[32];
struct mpi3_scsi_io_cdb_eedp32 eedp32; struct mpi3_scsi_io_cdb_eedp32 eedp32;
struct mpi3_sge_common sge; struct mpi3_sge_common sge;
...@@ -32,11 +32,12 @@ struct mpi3_scsi_io_request { ...@@ -32,11 +32,12 @@ struct mpi3_scsi_io_request {
__le32 skip_count; __le32 skip_count;
__le32 data_length; __le32 data_length;
u8 lun[8]; u8 lun[8];
union mpi3_scso_io_cdb_union cdb; union mpi3_scsi_io_cdb_union cdb;
union mpi3_sge_union sgl[4]; union mpi3_sge_union sgl[4];
}; };
#define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80) #define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID (0x80)
#define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE (0x40)
#define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000) #define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000)
#define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000) #define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000)
#define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000) #define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000)
...@@ -155,5 +156,13 @@ struct mpi3_scsi_task_mgmt_reply { ...@@ -155,5 +156,13 @@ struct mpi3_scsi_task_mgmt_reply {
__le32 reserved18; __le32 reserved18;
}; };
#define MPI3_SCSITASKMGMT_RSPCODE_TM_COMPLETE (0x00)
#define MPI3_SCSITASKMGMT_RSPCODE_INVALID_FRAME (0x02)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FUNCTION_NOT_SUPPORTED (0x04)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_FAILED (0x05)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_SUCCEEDED (0x08)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_INVALID_LUN (0x09)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_OVERLAPPED_TAG (0x0a)
#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80) #define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC (0x80)
#define MPI3_SCSITASKMGMT_RSPCODE_TM_NVME_DENIED (0x81)
#endif #endif
drivers/scsi/mpi3mr/mpi/mpi30_ioc.h
浏览文件 @ ec5ebd2c
...@@ -29,6 +29,11 @@ struct mpi3_ioc_init_request { ...@@ -29,6 +29,11 @@ struct mpi3_ioc_init_request {
__le64 driver_information_address; __le64 driver_information_address;
}; };
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03)
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00)
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01)
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02)
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03)
#define MPI3_WHOINIT_NOT_INITIALIZED (0x00) #define MPI3_WHOINIT_NOT_INITIALIZED (0x00)
#define MPI3_WHOINIT_ROM_BIOS (0x02) #define MPI3_WHOINIT_ROM_BIOS (0x02)
#define MPI3_WHOINIT_HOST_DRIVER (0x03) #define MPI3_WHOINIT_HOST_DRIVER (0x03)
...@@ -77,17 +82,17 @@ struct mpi3_ioc_facts_data { ...@@ -77,17 +82,17 @@ struct mpi3_ioc_facts_data {
u8 sge_modifier_shift; u8 sge_modifier_shift;
u8 protocol_flags; u8 protocol_flags;
__le16 max_sas_initiators; __le16 max_sas_initiators;
__le16 max_sas_targets; __le16 reserved2a;
__le16 max_sas_expanders; __le16 max_sas_expanders;
__le16 max_enclosures; __le16 max_enclosures;
__le16 min_dev_handle; __le16 min_dev_handle;
__le16 max_dev_handle; __le16 max_dev_handle;
__le16 max_pc_ie_switches; __le16 max_pcie_switches;
__le16 max_nvme; __le16 max_nvme;
__le16 max_pds; __le16 reserved38;
__le16 max_vds; __le16 max_vds;
__le16 max_host_pds; __le16 max_host_pds;
__le16 max_advanced_host_pds; __le16 max_adv_host_pds;
__le16 max_raid_pds; __le16 max_raid_pds;
__le16 max_posted_cmd_buffers; __le16 max_posted_cmd_buffers;
__le32 flags; __le32 flags;
...@@ -97,26 +102,41 @@ struct mpi3_ioc_facts_data { ...@@ -97,26 +102,41 @@ struct mpi3_ioc_facts_data {
__le16 reserved4e; __le16 reserved4e;
__le32 diag_trace_size; __le32 diag_trace_size;
__le32 diag_fw_size; __le32 diag_fw_size;
__le32 diag_driver_size;
u8 max_host_pd_ns_count;
u8 max_adv_host_pd_ns_count;
u8 max_raidpd_ns_count;
u8 reserved5f;
}; };
#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD (0x00000010) #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000)
#define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000)
#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x10000000)
#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE (0x00000100)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED (0x00000080)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED (0x00000040)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED (0x00000020)
#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED (0x00000010)
#define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008) #define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008)
#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_GRAN_MASK (0x00000001) #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED (0x00000002)
#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_IOC_GRAN (0x00000000) #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001)
#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_REPLY_Q_GRAN (0x00000001)
#define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000) #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000)
#define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12)
#define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00) #define MPI3_IOCFACTS_PID_PRODUCT_MASK (0x0f00)
#define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8) #define MPI3_IOCFACTS_PID_PRODUCT_SHIFT (8)
#define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff) #define MPI3_IOCFACTS_PID_FAMILY_MASK (0x00ff)
#define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0) #define MPI3_IOCFACTS_PID_FAMILY_SHIFT (0)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_REKEY (0x2000)
#define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000)
#define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_RAID (0x0100) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0200) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_RAID (0x0300) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_MGMT (0x0300)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0400) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_OOB (0x0400)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_OOB (0x0500)
#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_DRIVE_EXT_VIA_OOB (0x0600)
#define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080) #define MPI3_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0080)
#define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040) #define MPI3_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0040)
#define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020)
...@@ -175,6 +195,7 @@ struct mpi3_create_request_queue_request { ...@@ -175,6 +195,7 @@ struct mpi3_create_request_queue_request {
#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80)
#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80)
#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00)
#define MPI3_CREATE_REQUEST_QUEUE_SIZE_MINIMUM (2)
struct mpi3_delete_request_queue_request { struct mpi3_delete_request_queue_request {
__le16 host_tag; __le16 host_tag;
u8 ioc_use_only02; u8 ioc_use_only02;
...@@ -210,6 +231,7 @@ struct mpi3_create_reply_queue_request { ...@@ -210,6 +231,7 @@ struct mpi3_create_reply_queue_request {
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01)
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00)
#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01)
#define MPI3_CREATE_REPLY_QUEUE_SIZE_MINIMUM (2)
struct mpi3_delete_reply_queue_request { struct mpi3_delete_reply_queue_request {
__le16 host_tag; __le16 host_tag;
u8 ioc_use_only02; u8 ioc_use_only02;
...@@ -255,7 +277,9 @@ struct mpi3_port_enable_request { ...@@ -255,7 +277,9 @@ struct mpi3_port_enable_request {
#define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19) #define MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x19)
#define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20) #define MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x20)
#define MPI3_EVENT_PCIE_ENUMERATION (0x22) #define MPI3_EVENT_PCIE_ENUMERATION (0x22)
#define MPI3_EVENT_PCIE_ERROR_THRESHOLD (0x23)
#define MPI3_EVENT_HARD_RESET_RECEIVED (0x40) #define MPI3_EVENT_HARD_RESET_RECEIVED (0x40)
#define MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE (0x50)
#define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60) #define MPI3_EVENT_MIN_PRODUCT_SPECIFIC (0x60)
#define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f) #define MPI3_EVENT_MAX_PRODUCT_SPECIFIC (0x7f)
#define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4) #define MPI3_EVENT_NOTIFY_EVENTMASK_WORDS (4)
...@@ -311,10 +335,9 @@ struct mpi3_event_data_temp_threshold { ...@@ -311,10 +335,9 @@ struct mpi3_event_data_temp_threshold {
__le32 reserved0c; __le32 reserved0c;
}; };
#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD3_EXCEEDED (0x0008) #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_FATAL_THRESHOLD_EXCEEDED (0x0004)
#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD2_EXCEEDED (0x0004) #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_CRITICAL_THRESHOLD_EXCEEDED (0x0002)
#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD1_EXCEEDED (0x0002) #define MPI3_EVENT_TEMP_THRESHOLD_STATUS_WARNING_THRESHOLD_EXCEEDED (0x0001)
#define MPI3_EVENT_TEMP_THRESHOLD_STATUS_THRESHOLD0_EXCEEDED (0x0001)
struct mpi3_event_data_cable_management { struct mpi3_event_data_cable_management {
__le32 active_cable_power_requirement; __le32 active_cable_power_requirement;
u8 status; u8 status;
...@@ -398,8 +421,10 @@ struct mpi3_event_data_sas_discovery { ...@@ -398,8 +421,10 @@ struct mpi3_event_data_sas_discovery {
#define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000) #define MPI3_SAS_DISC_STATUS_MAX_EXPANDERS_EXCEED (0x40000000)
#define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000) #define MPI3_SAS_DISC_STATUS_MAX_DEVICES_EXCEED (0x20000000)
#define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000) #define MPI3_SAS_DISC_STATUS_MAX_TOPO_PHYS_EXCEED (0x10000000)
#define MPI3_SAS_DISC_STATUS_INVALID_CEI (0x00010000)
#define MPI3_SAS_DISC_STATUS_FECEI_MISMATCH (0x00008000)
#define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000) #define MPI3_SAS_DISC_STATUS_MULTIPLE_DEVICES_IN_SLOT (0x00004000)
#define MPI3_SAS_DISC_STATUS_SLOT_COUNT_MISMATCH (0x00002000) #define MPI3_SAS_DISC_STATUS_NECEI_MISMATCH (0x00002000)
#define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000) #define MPI3_SAS_DISC_STATUS_TOO_MANY_SLOTS (0x00001000)
#define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800) #define MPI3_SAS_DISC_STATUS_EXP_MULTI_SUBTRACTIVE (0x00000800)
#define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400) #define MPI3_SAS_DISC_STATUS_MULTI_PORT_DOMAIN (0x00000400)
...@@ -581,6 +606,20 @@ struct mpi3_event_data_pcie_topology_change_list { ...@@ -581,6 +606,20 @@ struct mpi3_event_data_pcie_topology_change_list {
#define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) #define MPI3_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
#define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) #define MPI3_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
#define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) #define MPI3_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
struct mpi3_event_data_pcie_error_threshold {
__le64 timestamp;
u8 reason_code;
u8 port;
__le16 switch_dev_handle;
u8 error;
u8 action;
__le16 threshold_count;
__le16 attached_dev_handle;
__le16 reserved12;
};
#define MPI3_EVENT_PCI_ERROR_RC_THRESHOLD_EXCEEDED (0x00)
#define MPI3_EVENT_PCI_ERROR_RC_ESCALATION (0x01)
struct mpi3_event_data_sas_init_dev_status_change { struct mpi3_event_data_sas_init_dev_status_change {
u8 reason_code; u8 reason_code;
u8 io_unit_port; u8 io_unit_port;
...@@ -604,6 +643,16 @@ struct mpi3_event_data_hard_reset_received { ...@@ -604,6 +643,16 @@ struct mpi3_event_data_hard_reset_received {
__le16 reserved02; __le16 reserved02;
}; };
struct mpi3_event_data_diag_buffer_status_change {
u8 type;
u8 reason_code;
__le16 reserved02;
__le32 reserved04;
};
#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RELEASED (0x01)
#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_PAUSED (0x02)
#define MPI3_EVENT_DIAG_BUFFER_STATUS_CHANGE_RC_RESUMED (0x03)
#define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200) #define MPI3_PEL_LOCALE_FLAGS_NON_BLOCKING_BOOT_EVENT (0x0200)
#define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100) #define MPI3_PEL_LOCALE_FLAGS_BLOCKING_BOOT_EVENT (0x0100)
#define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080) #define MPI3_PEL_LOCALE_FLAGS_PCIE (0x0080)
...@@ -645,21 +694,23 @@ struct mpi3_pel_seq { ...@@ -645,21 +694,23 @@ struct mpi3_pel_seq {
}; };
struct mpi3_pel_entry { struct mpi3_pel_entry {
__le64 time_stamp;
__le32 sequence_number; __le32 sequence_number;
__le32 time_stamp[2];
__le16 log_code; __le16 log_code;
__le16 arg_type; __le16 arg_type;
__le16 locale; __le16 locale;
u8 class; u8 class;
u8 reserved13; u8 flags;
u8 ext_num; u8 ext_num;
u8 num_exts; u8 num_exts;
u8 arg_data_size; u8 arg_data_size;
u8 fixed_format_size; u8 fixed_format_strings_size;
__le32 reserved18[2]; __le32 reserved18[2];
__le32 pel_info[24]; __le32 pel_info[24];
}; };
#define MPI3_PEL_FLAGS_COMPLETE_RESET_NEEDED (0x02)
#define MPI3_PEL_FLAGS_ACK_NEEDED (0x01)
struct mpi3_pel_list { struct mpi3_pel_list {
__le32 log_count; __le32 log_count;
__le32 reserved04; __le32 reserved04;
...@@ -837,7 +888,10 @@ struct mpi3_pel_req_action_acknowledge { ...@@ -837,7 +888,10 @@ struct mpi3_pel_req_action_acknowledge {
__le32 reserved10; __le32 reserved10;
}; };
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT (0x01) #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03)
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00)
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01)
#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02)
struct mpi3_pel_reply { struct mpi3_pel_reply {
__le16 host_tag; __le16 host_tag;
u8 ioc_use_only02; u8 ioc_use_only02;
...@@ -885,6 +939,7 @@ struct mpi3_ci_download_request { ...@@ -885,6 +939,7 @@ struct mpi3_ci_download_request {
#define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02) #define MPI3_CI_DOWNLOAD_ACTION_ONLINE_ACTIVATION (0x02)
#define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03) #define MPI3_CI_DOWNLOAD_ACTION_OFFLINE_ACTIVATION (0x03)
#define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04) #define MPI3_CI_DOWNLOAD_ACTION_GET_STATUS (0x04)
#define MPI3_CI_DOWNLOAD_ACTION_CANCEL_OFFLINE_ACTIVATION (0x05)
struct mpi3_ci_download_reply { struct mpi3_ci_download_reply {
__le16 host_tag; __le16 host_tag;
u8 ioc_use_only02; u8 ioc_use_only02;
...@@ -902,6 +957,7 @@ struct mpi3_ci_download_reply { ...@@ -902,6 +957,7 @@ struct mpi3_ci_download_reply {
}; };
#define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80) #define MPI3_CI_DOWNLOAD_FLAGS_DOWNLOAD_IN_PROGRESS (0x80)
#define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20)
#define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10)
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0e)
#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00)
...@@ -939,19 +995,28 @@ struct mpi3_ci_upload_request { ...@@ -939,19 +995,28 @@ struct mpi3_ci_upload_request {
#define MPI3_CTRL_OP_REMOVE_DEVICE (0x10) #define MPI3_CTRL_OP_REMOVE_DEVICE (0x10)
#define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11) #define MPI3_CTRL_OP_CLOSE_PERSISTENT_CONNECTION (0x11)
#define MPI3_CTRL_OP_HIDDEN_ACK (0x12) #define MPI3_CTRL_OP_HIDDEN_ACK (0x12)
#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS (0x13)
#define MPI3_CTRL_OP_SAS_SEND_PRIMITIVE (0x20) #define MPI3_CTRL_OP_SAS_SEND_PRIMITIVE (0x20)
#define MPI3_CTRL_OP_SAS_CLEAR_ERROR_LOG (0x21) #define MPI3_CTRL_OP_SAS_PHY_CONTROL (0x21)
#define MPI3_CTRL_OP_PCIE_CLEAR_ERROR_LOG (0x22) #define MPI3_CTRL_OP_READ_INTERNAL_BUS (0x23)
#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS (0x24)
#define MPI3_CTRL_OP_PCIE_LINK_CONTROL (0x30)
#define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00) #define MPI3_CTRL_OP_LOOKUP_MAPPING_PARAM8_LOOKUP_METHOD_INDEX (0x00)
#define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00) #define MPI3_CTRL_OP_UPDATE_TIMESTAMP_PARAM64_TIMESTAMP_INDEX (0x00)
#define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00) #define MPI3_CTRL_OP_REMOVE_DEVICE_PARAM16_DEVHANDLE_INDEX (0x00)
#define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00) #define MPI3_CTRL_OP_CLOSE_PERSIST_CONN_PARAM16_DEVHANDLE_INDEX (0x00)
#define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00) #define MPI3_CTRL_OP_HIDDEN_ACK_PARAM16_DEVHANDLE_INDEX (0x00)
#define MPI3_CTRL_OP_CLEAR_DEVICE_COUNTERS_PARAM16_DEVHANDLE_INDEX (0x00)
#define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PHY_INDEX (0x00) #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PHY_INDEX (0x00)
#define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PRIMSEQ_INDEX (0x01) #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM8_PRIMSEQ_INDEX (0x01)
#define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM32_PRIMITIVE_INDEX (0x00) #define MPI3_CTRL_OP_SAS_SEND_PRIM_PARAM32_PRIMITIVE_INDEX (0x00)
#define MPI3_CTRL_OP_SAS_CLEAR_ERR_LOG_PARAM8_PHY_INDEX (0x00) #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_ACTION_INDEX (0x00)
#define MPI3_CTRL_OP_PCIE_CLEAR_ERR_LOG_PARAM8_PHY_INDEX (0x00) #define MPI3_CTRL_OP_SAS_PHY_CONTROL_PARAM8_PHY_INDEX (0x01)
#define MPI3_CTRL_OP_READ_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00)
#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM64_ADDRESS_INDEX (0x00)
#define MPI3_CTRL_OP_WRITE_INTERNAL_BUS_PARAM32_VALUE_INDEX (0x00)
#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_ACTION_INDEX (0x00)
#define MPI3_CTRL_OP_PCIE_LINK_CONTROL_PARAM8_LINK_INDEX (0x01)
#define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) #define MPI3_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
#define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) #define MPI3_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
#define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) #define MPI3_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
...@@ -966,9 +1031,14 @@ struct mpi3_ci_upload_request { ...@@ -966,9 +1031,14 @@ struct mpi3_ci_upload_request {
#define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1) #define MPI3_CTRL_LOOKUP_METHOD_PERSISTID_PARAM16_PERSISTENT_ID_INDEX (1)
#define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0) #define MPI3_CTRL_LOOKUP_METHOD_VALUE16_DEVH_INDEX (0)
#define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0) #define MPI3_CTRL_GET_TIMESTAMP_VALUE64_TIMESTAMP_INDEX (0)
#define MPI3_CTRL_READ_INTERNAL_BUS_VALUE32_VALUE_INDEX (0)
#define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01) #define MPI3_CTRL_PRIMFLAGS_SINGLE (0x01)
#define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03) #define MPI3_CTRL_PRIMFLAGS_TRIPLE (0x03)
#define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06) #define MPI3_CTRL_PRIMFLAGS_REDUNDANT (0x06)
#define MPI3_CTRL_ACTION_NOP (0x00)
#define MPI3_CTRL_ACTION_LINK_RESET (0x01)
#define MPI3_CTRL_ACTION_HARD_RESET (0x02)
#define MPI3_CTRL_ACTION_CLEAR_ERROR_LOG (0x05)
struct mpi3_iounit_control_request { struct mpi3_iounit_control_request {
__le16 host_tag; __le16 host_tag;
u8 ioc_use_only02; u8 ioc_use_only02;
......
drivers/scsi/mpi3mr/mpi/mpi30_pci.h 0 → 100644
浏览文件 @ ec5ebd2c
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016-2021 Broadcom Inc. All rights reserved.
*
*/
#ifndef MPI30_PCI_H
#define MPI30_PCI_H 1
#ifndef MPI3_NVME_ENCAP_CMD_MAX
#define MPI3_NVME_ENCAP_CMD_MAX (1)
#endif
struct mpi3_nvme_encapsulated_request {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 change_count;
__le16 dev_handle;
__le16 encapsulated_command_length;
__le16 flags;
__le32 reserved10[4];
__le32 command[MPI3_NVME_ENCAP_CMD_MAX];
};
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002)
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000)
#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002)
#define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK (0x0001)
#define MPI3_NVME_FLAGS_SUBMISSIONQ_IO (0x0000)
#define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0001)
struct mpi3_nvme_encapsulated_error_reply {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 ioc_use_only08;
__le16 ioc_status;
__le32 ioc_log_info;
__le32 nvme_completion_entry[4];
};
#endif
drivers/scsi/mpi3mr/mpi/mpi30_sas.h
浏览文件 @ ec5ebd2c
...@@ -30,4 +30,18 @@ struct mpi3_smp_passthrough_request { ...@@ -30,4 +30,18 @@ struct mpi3_smp_passthrough_request {
struct mpi3_sge_common request_sge; struct mpi3_sge_common request_sge;
struct mpi3_sge_common response_sge; struct mpi3_sge_common response_sge;
}; };
struct mpi3_smp_passthrough_reply {
__le16 host_tag;
u8 ioc_use_only02;
u8 function;
__le16 ioc_use_only04;
u8 ioc_use_only06;
u8 msg_flags;
__le16 ioc_use_only08;
__le16 ioc_status;
__le32 ioc_log_info;
__le16 response_data_length;
__le16 reserved12;
};
#endif #endif
drivers/scsi/mpi3mr/mpi/mpi30_transport.h
浏览文件 @ ec5ebd2c
...@@ -19,8 +19,8 @@ union mpi3_version_union { ...@@ -19,8 +19,8 @@ union mpi3_version_union {
#define MPI3_VERSION_MAJOR (3) #define MPI3_VERSION_MAJOR (3)
#define MPI3_VERSION_MINOR (0) #define MPI3_VERSION_MINOR (0)
#define MPI3_VERSION_UNIT (0) #define MPI3_VERSION_UNIT (22)
#define MPI3_VERSION_DEV (18) #define MPI3_VERSION_DEV (0)
struct mpi3_sysif_oper_queue_indexes { struct mpi3_sysif_oper_queue_indexes {
__le16 producer_index; __le16 producer_index;
__le16 reserved02; __le16 reserved02;
...@@ -74,6 +74,7 @@ struct mpi3_sysif_registers { ...@@ -74,6 +74,7 @@ struct mpi3_sysif_registers {
#define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004) #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004)
#define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000) #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000)
#define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24) #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24)
#define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001)
#define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014) #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014)
#define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00f00000) #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00f00000)
#define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20) #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20)
...@@ -82,12 +83,13 @@ struct mpi3_sysif_registers { ...@@ -82,12 +83,13 @@ struct mpi3_sysif_registers {
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000c000) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000c000)
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000)
#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000)
#define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN (0x00002000) #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000)
#define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010) #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010)
#define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001) #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001)
#define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001c) #define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001c)
#define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010) #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000c) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000c)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT (0x00000002)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004)
#define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008) #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008)
...@@ -107,9 +109,9 @@ struct mpi3_sysif_registers { ...@@ -107,9 +109,9 @@ struct mpi3_sysif_registers {
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000)
#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xc0000000) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xc0000000)
#define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x30000000) #define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x20000000)
#define MPI3_SYSIF_COALESCE_CONTROL_QUEUE_ID_MASK (0x00ff0000) #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK (0x01ff0000)
#define MPI3_SYSIF_COALESCE_CONTROL_QUEUE_ID_SHIFT (16) #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT (16)
#define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000ff00) #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000ff00)
#define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8) #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8)
#define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000ff) #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000ff)
...@@ -117,9 +119,9 @@ struct mpi3_sysif_registers { ...@@ -117,9 +119,9 @@ struct mpi3_sysif_registers {
#define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000) #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000)
#define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004) #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004)
#define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008) #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008)
#define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(n) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((n) - 1) * 8)) #define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N) - 1) * 8))
#define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100c) #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100c)
#define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(n) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((n) - 1) * 8)) #define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N) - 1) * 8))
#define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001c04) #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001c04)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000f) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000f)
#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0)
...@@ -133,7 +135,7 @@ struct mpi3_sysif_registers { ...@@ -133,7 +135,7 @@ struct mpi3_sysif_registers {
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_FLASH_RCVRY_RESET (0x00000200) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300)
#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700)
#define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080) #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080)
...@@ -153,8 +155,9 @@ struct mpi3_sysif_registers { ...@@ -153,8 +155,9 @@ struct mpi3_sysif_registers {
#define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000f001) #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000f001)
#define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000f002) #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000f002)
#define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000f003) #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000f003)
#define MPI3_SYSIF_FAULT_CODE_SAFE_MODE_EXIT (0x0000f004) #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000f004)
#define MPI3_SYSIF_FAULT_CODE_FACTORY_RESET (0x0000f005) #define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000f005)
#define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000f006)
#define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001c14) #define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001c14)
#define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001c18) #define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001c18)
#define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001c1c) #define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001c1c)
...@@ -409,6 +412,8 @@ struct mpi3_default_reply { ...@@ -409,6 +412,8 @@ struct mpi3_default_reply {
#define MPI3_IOCSTATUS_INVALID_STATE (0x0008) #define MPI3_IOCSTATUS_INVALID_STATE (0x0008)
#define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000a) #define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000a)
#define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000b) #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000b)
#define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000c)
#define MPI3_IOCSTATUS_SUPERVISOR_ONLY (0x000d)
#define MPI3_IOCSTATUS_FAILURE (0x001f) #define MPI3_IOCSTATUS_FAILURE (0x001f)
#define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
#define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
...@@ -448,8 +453,10 @@ struct mpi3_default_reply { ...@@ -448,8 +453,10 @@ struct mpi3_default_reply {
#define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00b0) #define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00b0)
#define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00b1) #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00b1)
#define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00b2) #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00b2)
#define MPI3_IOCSTATUS_CI_UPDATE_PENDING (0x00b3) #define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING (0x00b3)
#define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE (0x00b4)
#define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00c0) #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00c0)
#define MPI3_IOCSTATUS_SECURITY_VIOLATION (0x00c1)
#define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0f00) #define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0f00)
#define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0f01) #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0f01)
#define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0f02) #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0f02)
......
drivers/scsi/mpi3mr/mpi3mr.h
浏览文件 @ ec5ebd2c
...@@ -45,6 +45,7 @@ ...@@ -45,6 +45,7 @@
#include "mpi/mpi30_init.h" #include "mpi/mpi30_init.h"
#include "mpi/mpi30_ioc.h" #include "mpi/mpi30_ioc.h"
#include "mpi/mpi30_sas.h" #include "mpi/mpi30_sas.h"
#include "mpi/mpi30_pci.h"
#include "mpi3mr_debug.h" #include "mpi3mr_debug.h"
/* Global list and lock for storing multiple adapters managed by the driver */ /* Global list and lock for storing multiple adapters managed by the driver */
...@@ -121,7 +122,7 @@ extern int prot_mask; ...@@ -121,7 +122,7 @@ extern int prot_mask;
/* Definitions for Event replies and sense buffer allocated per controller */ /* Definitions for Event replies and sense buffer allocated per controller */
#define MPI3MR_NUM_EVT_REPLIES 64 #define MPI3MR_NUM_EVT_REPLIES 64
#define MPI3MR_SENSEBUF_SZ 256 #define MPI3MR_SENSE_BUF_SZ 256
#define MPI3MR_SENSEBUF_FACTOR 3 #define MPI3MR_SENSEBUF_FACTOR 3
#define MPI3MR_CHAINBUF_FACTOR 3 #define MPI3MR_CHAINBUF_FACTOR 3
#define MPI3MR_CHAINBUFDIX_FACTOR 2 #define MPI3MR_CHAINBUFDIX_FACTOR 2
...@@ -263,7 +264,7 @@ struct mpi3mr_ioc_facts { ...@@ -263,7 +264,7 @@ struct mpi3mr_ioc_facts {
u16 max_vds; u16 max_vds;
u16 max_hpds; u16 max_hpds;
u16 max_advhpds; u16 max_advhpds;
u16 max_raidpds; u16 max_raid_pds;
u16 min_devhandle; u16 min_devhandle;
u16 max_devhandle; u16 max_devhandle;
u16 max_op_req_q; u16 max_op_req_q;
......
drivers/scsi/mpi3mr/mpi3mr_fw.c
浏览文件 @ ec5ebd2c
...@@ -2012,7 +2012,7 @@ static void mpi3mr_watchdog_work(struct work_struct *work) ...@@ -2012,7 +2012,7 @@ static void mpi3mr_watchdog_work(struct work_struct *work)
mpi3mr_print_fault_info(mrioc); mpi3mr_print_fault_info(mrioc);
mrioc->diagsave_timeout = 0; mrioc->diagsave_timeout = 0;
if (fault == MPI3_SYSIF_FAULT_CODE_FACTORY_RESET) { if (fault == MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED) {
ioc_info(mrioc, ioc_info(mrioc,
"Factory Reset fault occurred marking controller as unrecoverable" "Factory Reset fault occurred marking controller as unrecoverable"
); );
...@@ -2377,14 +2377,13 @@ static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, ...@@ -2377,14 +2377,13 @@ static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4; mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions); mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id); mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
mrioc->facts.max_pds = le16_to_cpu(facts_data->max_pds);
mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds); mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds); mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_advanced_host_pds); mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
mrioc->facts.max_raidpds = le16_to_cpu(facts_data->max_raid_pds); mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme); mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
mrioc->facts.max_pcie_switches = mrioc->facts.max_pcie_switches =
le16_to_cpu(facts_data->max_pc_ie_switches); le16_to_cpu(facts_data->max_pcie_switches);
mrioc->facts.max_sasexpanders = mrioc->facts.max_sasexpanders =
le16_to_cpu(facts_data->max_sas_expanders); le16_to_cpu(facts_data->max_sas_expanders);
mrioc->facts.max_sasinitiators = mrioc->facts.max_sasinitiators =
...@@ -2418,10 +2417,9 @@ static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, ...@@ -2418,10 +2417,9 @@ static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
mrioc->facts.ioc_num, mrioc->facts.max_op_req_q, mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle); mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
ioc_info(mrioc, ioc_info(mrioc,
"maxreqs(%d), mindh(%d) maxPDs(%d) maxvectors(%d) maxperids(%d)\n", "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
mrioc->facts.max_reqs, mrioc->facts.min_devhandle, mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
mrioc->facts.max_pds, mrioc->facts.max_msix_vectors, mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
mrioc->facts.max_perids);
ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ", ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value, mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
mrioc->facts.sge_mod_shift); mrioc->facts.sge_mod_shift);
...@@ -2520,7 +2518,7 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) ...@@ -2520,7 +2518,7 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
goto out_failed; goto out_failed;
/* sense buffer pool, 4 byte align */ /* sense buffer pool, 4 byte align */
sz = mrioc->num_sense_bufs * MPI3MR_SENSEBUF_SZ; sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
mrioc->sense_buf_pool = dma_pool_create("sense_buf pool", mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
&mrioc->pdev->dev, sz, 4, 0); &mrioc->pdev->dev, sz, 4, 0);
if (!mrioc->sense_buf_pool) { if (!mrioc->sense_buf_pool) {
...@@ -2556,10 +2554,10 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) ...@@ -2556,10 +2554,10 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
"reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n", "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024), mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
(unsigned long long)mrioc->reply_free_q_dma); (unsigned long long)mrioc->reply_free_q_dma);
sz = mrioc->num_sense_bufs * MPI3MR_SENSEBUF_SZ; sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
ioc_info(mrioc, ioc_info(mrioc,
"sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n", "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSEBUF_SZ, mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
(sz / 1024), (unsigned long long)mrioc->sense_buf_dma); (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
sz = mrioc->sense_buf_q_sz * 8; sz = mrioc->sense_buf_q_sz * 8;
ioc_info(mrioc, ioc_info(mrioc,
...@@ -2575,7 +2573,7 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc) ...@@ -2575,7 +2573,7 @@ static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
/* initialize Sense Buffer Queue */ /* initialize Sense Buffer Queue */
for (i = 0, phy_addr = mrioc->sense_buf_dma; for (i = 0, phy_addr = mrioc->sense_buf_dma;
i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSEBUF_SZ) i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr); mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
mrioc->sense_buf_q[i] = cpu_to_le64(0); mrioc->sense_buf_q[i] = cpu_to_le64(0);
return retval; return retval;
...@@ -2642,7 +2640,7 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) ...@@ -2642,7 +2640,7 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz); iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
iocinit_req.reply_free_queue_address = iocinit_req.reply_free_queue_address =
cpu_to_le64(mrioc->reply_free_q_dma); cpu_to_le64(mrioc->reply_free_q_dma);
iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSEBUF_SZ); iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
iocinit_req.sense_buffer_free_queue_depth = iocinit_req.sense_buffer_free_queue_depth =
cpu_to_le16(mrioc->sense_buf_q_sz); cpu_to_le16(mrioc->sense_buf_q_sz);
iocinit_req.sense_buffer_free_queue_address = iocinit_req.sense_buffer_free_queue_address =
...@@ -3667,7 +3665,7 @@ static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc) ...@@ -3667,7 +3665,7 @@ static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN; ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
......
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