RISC-V: probes: Treat the instruction stream as host-endian

mainline inclusion
from mainline-v5.19
commit 5dd67133
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5QM0N
CVE: NA

-------------------------------------------------

Neither of these are actually correct: the instruction stream is defined
(for versions of the ISA manual newer than 2.2) as a stream of 16-bit
little-endian parcels, which is different than just being little-endian.
In theory we should represent this as a type, but we don't have any
concrete plans for the big endian stuff so it doesn't seem worth the
time -- we've got variants of this all over the place.

Instead I'm just dropping the unnecessary type conversion, which is a
NOP on LE systems but causes an sparse error as the types are all mixed
up.
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>
Acked-by: NGuo Ren <guoren@kernel.org>
Signed-off-by: NPalmer Dabbelt <palmerdabbelt@google.com>

arch/riscv/kernel/probes/decode-insn.c

@@ -16,7 +16,7 @@
 enum probe_insn __kprobes
 riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
 {
-	probe_opcode_t insn = le32_to_cpu(*addr);
+	probe_opcode_t insn = *addr;
 
 	/*
 	 * Reject instructions list:

arch/riscv/kernel/probes/kprobes.c

@@ -57,7 +57,7 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
 	}
 
 	/* copy instruction */
-	p->opcode = le32_to_cpu(*p->addr);
+	p->opcode = *p->addr;
 
 	/* decode instruction */
 	switch (riscv_probe_decode_insn(p->addr, &p->ainsn.api)) {