提交 e6a07712 编写于 作者: C Chiqijun 提交者: Yang Yingliang

net/hinic: Fix alignment and code style

driver inclusion
category: bugfix
bugzilla: 4472

-----------------------------------------------------------------------

Fix alignment and code style.
Signed-off-by: NChiqijun <chiqijun@huawei.com>
Reviewed-by: NZengweiliang <zengweiliang.zengweiliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 0389e4b3
......@@ -561,7 +561,6 @@ static void parse_dev_cap(struct hinic_hwdev *dev,
if (IS_NIC_TYPE(dev))
parse_l2nic_res_cap(dev, cap, dev_cap, type);
/* FCoE/IOE/TOE/FC without virtulization */
if (type == TYPE_PF || type == TYPE_PPF) {
if (IS_FC_TYPE(dev))
......@@ -677,7 +676,6 @@ static void nic_param_fix(struct hinic_hwdev *dev)
nic_cap->max_rqs = nic_cap->max_queue_allowed;
nic_cap->max_sqs = nic_cap->max_queue_allowed;
}
}
static void rdma_param_fix(struct hinic_hwdev *dev)
......@@ -1546,8 +1544,8 @@ void free_cfg_mgmt(struct hinic_hwdev *dev)
int init_capability(struct hinic_hwdev *dev)
{
int err;
struct cfg_mgmt_info *cfg_mgmt = dev->cfg_mgmt;
int err;
set_cfg_test_param(cfg_mgmt);
......@@ -2153,6 +2151,7 @@ static void hinic_os_dep_deinit(struct hinic_hwdev *hwdev)
void hinic_ppf_hwdev_unreg(void *hwdev)
{
struct hinic_hwdev *dev = hwdev;
if (!hwdev)
return;
......@@ -2166,6 +2165,7 @@ void hinic_ppf_hwdev_unreg(void *hwdev)
void hinic_ppf_hwdev_reg(void *hwdev, void *ppf_hwdev)
{
struct hinic_hwdev *dev = hwdev;
if (!hwdev)
return;
......
......@@ -54,7 +54,7 @@
#define CMDQ_DB_INFO_SRC_TYPE_MASK 0x1FU
#define CMDQ_DB_INFO_SET(val, member) \
((val & CMDQ_DB_INFO_##member##_MASK) \
(((val) & CMDQ_DB_INFO_##member##_MASK) \
<< CMDQ_DB_INFO_##member##_SHIFT)
#define CMDQ_CTRL_PI_SHIFT 0
......@@ -169,7 +169,7 @@
#define CMDQ_DB_PI_OFF(pi) (((u16)LOWER_8_BITS(pi)) << 3)
#define CMDQ_DB_ADDR(db_base, pi) \
(((u8 *)db_base + HINIC_DB_OFF) + CMDQ_DB_PI_OFF(pi))
(((u8 *)(db_base) + HINIC_DB_OFF) + CMDQ_DB_PI_OFF(pi))
#define CMDQ_PFN_SHIFT 12
#define CMDQ_PFN(addr) ((addr) >> CMDQ_PFN_SHIFT)
......
......@@ -92,12 +92,12 @@
(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
#define HINIC_EQ_HI_PHYS_ADDR_REG(type, q_id, pg_num) \
((u32)((type == HINIC_AEQ) ? \
((u32)(((type) == HINIC_AEQ) ? \
HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) : \
HINIC_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))
#define HINIC_EQ_LO_PHYS_ADDR_REG(type, q_id, pg_num) \
((u32)((type == HINIC_AEQ) ? \
((u32)(((type) == HINIC_AEQ) ? \
HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) : \
HINIC_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))
......
......@@ -29,7 +29,7 @@
((ALIGN(((max_sge) - 2), 4) / 4 + 1) * (wqebb_size)))
/* performance: ci addr RTE_CACHE_SIZE(64B) alignment */
#define HINIC_CI_Q_ADDR_SIZE (64)
#define HINIC_CI_Q_ADDR_SIZE 64
#define CI_TABLE_SIZE(num_qps, pg_sz) \
(ALIGN((num_qps) * HINIC_CI_Q_ADDR_SIZE, pg_sz))
......@@ -67,8 +67,8 @@
#define SQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
#define SQ_CTXT_CEQ_ATTR_ARM_MASK 0x1U
#define SQ_CTXT_CEQ_ATTR_SET(val, member) (((val) & \
SQ_CTXT_CEQ_ATTR_##member##_MASK) \
#define SQ_CTXT_CEQ_ATTR_SET(val, member) \
(((val) & SQ_CTXT_CEQ_ATTR_##member##_MASK) \
<< SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
#define SQ_CTXT_CI_IDX_SHIFT 11
......@@ -77,8 +77,8 @@
#define SQ_CTXT_CI_IDX_MASK 0xFFFU
#define SQ_CTXT_CI_OWNER_MASK 0x1U
#define SQ_CTXT_CI_SET(val, member) (((val) & \
SQ_CTXT_CI_##member##_MASK) \
#define SQ_CTXT_CI_SET(val, member) \
(((val) & SQ_CTXT_CI_##member##_MASK) \
<< SQ_CTXT_CI_##member##_SHIFT)
#define SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
......@@ -87,8 +87,8 @@
#define SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
#define SQ_CTXT_WQ_PAGE_PI_MASK 0xFFFU
#define SQ_CTXT_WQ_PAGE_SET(val, member) (((val) & \
SQ_CTXT_WQ_PAGE_##member##_MASK) \
#define SQ_CTXT_WQ_PAGE_SET(val, member) \
(((val) & SQ_CTXT_WQ_PAGE_##member##_MASK) \
<< SQ_CTXT_WQ_PAGE_##member##_SHIFT)
#define SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
......@@ -105,16 +105,16 @@
#define SQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
#define SQ_CTXT_PREF_CI_MASK 0xFFFU
#define SQ_CTXT_PREF_SET(val, member) (((val) & \
SQ_CTXT_PREF_##member##_MASK) \
#define SQ_CTXT_PREF_SET(val, member) \
(((val) & SQ_CTXT_PREF_##member##_MASK) \
<< SQ_CTXT_PREF_##member##_SHIFT)
#define SQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
#define SQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
#define SQ_CTXT_WQ_BLOCK_SET(val, member) (((val) & \
SQ_CTXT_WQ_BLOCK_##member##_MASK) \
#define SQ_CTXT_WQ_BLOCK_SET(val, member) \
(((val) & SQ_CTXT_WQ_BLOCK_##member##_MASK) \
<< SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
#define RQ_CTXT_CEQ_ATTR_EN_SHIFT 0
......@@ -123,8 +123,8 @@
#define RQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
#define RQ_CTXT_CEQ_ATTR_OWNER_MASK 0x1U
#define RQ_CTXT_CEQ_ATTR_SET(val, member) (((val) & \
RQ_CTXT_CEQ_ATTR_##member##_MASK) \
#define RQ_CTXT_CEQ_ATTR_SET(val, member) \
(((val) & RQ_CTXT_CEQ_ATTR_##member##_MASK) \
<< RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
#define RQ_CTXT_PI_IDX_SHIFT 0
......@@ -135,8 +135,8 @@
#define RQ_CTXT_PI_INTR_MASK 0x3FFU
#define RQ_CTXT_PI_CEQ_ARM_MASK 0x1U
#define RQ_CTXT_PI_SET(val, member) (((val) & \
RQ_CTXT_PI_##member##_MASK) << \
#define RQ_CTXT_PI_SET(val, member) \
(((val) & RQ_CTXT_PI_##member##_MASK) << \
RQ_CTXT_PI_##member##_SHIFT)
#define RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
......@@ -145,8 +145,8 @@
#define RQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
#define RQ_CTXT_WQ_PAGE_CI_MASK 0xFFFU
#define RQ_CTXT_WQ_PAGE_SET(val, member) (((val) & \
RQ_CTXT_WQ_PAGE_##member##_MASK) << \
#define RQ_CTXT_WQ_PAGE_SET(val, member) \
(((val) & RQ_CTXT_WQ_PAGE_##member##_MASK) << \
RQ_CTXT_WQ_PAGE_##member##_SHIFT)
#define RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
......@@ -163,16 +163,16 @@
#define RQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
#define RQ_CTXT_PREF_CI_MASK 0xFFFU
#define RQ_CTXT_PREF_SET(val, member) (((val) & \
RQ_CTXT_PREF_##member##_MASK) << \
#define RQ_CTXT_PREF_SET(val, member) \
(((val) & RQ_CTXT_PREF_##member##_MASK) << \
RQ_CTXT_PREF_##member##_SHIFT)
#define RQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
#define RQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
#define RQ_CTXT_WQ_BLOCK_SET(val, member) (((val) & \
RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
#define RQ_CTXT_WQ_BLOCK_SET(val, member) \
(((val) & RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
#define SIZE_16BYTES(size) (ALIGN((size), 16) >> 4)
......
......@@ -120,8 +120,6 @@ void hinic_init_ieee_settings(struct hinic_nic_dev *nic_dev)
if (dcb_cfg->tc_cfg[i].pfc_en)
pfc->pfc_en |= (u8)BIT(i);
}
return;
}
static int hinic_set_up_cos_map(struct hinic_nic_dev *nic_dev,
......
......@@ -1064,6 +1064,7 @@ static void free_eq_pages(struct hinic_eq *eq)
kfree(eq->virt_addr);
kfree(eq->dma_addr);
}
static inline u32 get_page_size(struct hinic_eq *eq)
{
u32 total_size;
......@@ -1087,6 +1088,7 @@ static inline u32 get_page_size(struct hinic_eq *eq)
return EQ_MIN_PAGE_SIZE << n;
}
/**
* init_eq - initialize eq
* @eq: the event queue
......
......@@ -71,6 +71,7 @@ struct hinic_eq_work {
struct hinic_ceq_tasklet_data {
void *data;
};
struct hinic_eq {
struct hinic_hwdev *hwdev;
u16 q_id;
......
......@@ -337,10 +337,10 @@ void hinic_get_io_stats(struct hinic_nic_dev *nic_dev,
}
}
#define LP_DEFAULT_TIME (5) /* seconds */
#define LP_PKT_LEN (1514)
#define OBJ_STR_MAX_LEN (32)
#define SET_LINK_STR_MAX_LEN (128)
#define LP_DEFAULT_TIME 5 /* seconds */
#define LP_PKT_LEN 1514
#define OBJ_STR_MAX_LEN 32
#define SET_LINK_STR_MAX_LEN 128
#define PORT_DOWN_ERR_IDX 0
enum diag_test_index {
......@@ -684,23 +684,23 @@ static int hinic_get_settings(struct net_device *netdev,
}
static int hinic_get_link_ksettings(struct net_device *netdev,
struct ethtool_link_ksettings *link_settings)
struct ethtool_link_ksettings *cmd)
{
struct cmd_link_settings settings = {0};
struct ethtool_link_settings *base = &link_settings->base;
struct ethtool_link_settings *base = &cmd->base;
int err;
ethtool_link_ksettings_zero_link_mode(link_settings, supported);
ethtool_link_ksettings_zero_link_mode(link_settings, advertising);
ethtool_link_ksettings_zero_link_mode(cmd, supported);
ethtool_link_ksettings_zero_link_mode(cmd, advertising);
err = get_link_settings(netdev, &settings);
if (err)
return err;
bitmap_copy(link_settings->link_modes.supported,
bitmap_copy(cmd->link_modes.supported,
(unsigned long *)&settings.supported,
__ETHTOOL_LINK_MODE_MASK_NBITS);
bitmap_copy(link_settings->link_modes.advertising,
bitmap_copy(cmd->link_modes.advertising,
(unsigned long *)&settings.advertising,
__ETHTOOL_LINK_MODE_MASK_NBITS);
......@@ -868,11 +868,11 @@ static int hinic_set_settings(struct net_device *netdev,
}
static int hinic_set_link_ksettings(struct net_device *netdev,
const struct ethtool_link_ksettings *link_settings)
const struct ethtool_link_ksettings *cmd)
{
/* Only support to set autoneg and speed */
return set_link_settings(netdev, link_settings->base.autoneg,
link_settings->base.speed);
return set_link_settings(netdev, cmd->base.autoneg,
cmd->base.speed);
}
static void hinic_get_drvinfo(struct net_device *netdev,
......@@ -1387,27 +1387,27 @@ static int is_coalesce_legal(struct net_device *netdev,
#define CHECK_COALESCE_ALIGN(coal, item, unit) \
do { \
if (coal->item % (unit)) \
if ((coal)->item % (unit)) \
nicif_warn(nic_dev, drv, netdev, \
"%s in %d units, change to %d\n", \
#item, (unit), ALIGN_DOWN(coal->item, unit));\
#item, (unit), ALIGN_DOWN((coal)->item, unit));\
} while (0)
#define CHECK_COALESCE_CHANGED(coal, item, unit, ori_val, obj_str) \
do { \
if ((coal->item / (unit)) != (ori_val)) \
if (((coal)->item / (unit)) != (ori_val)) \
nicif_info(nic_dev, drv, netdev, \
"Change %s from %d to %d %s\n", \
#item, (ori_val) * (unit), \
ALIGN_DOWN(coal->item, unit), (obj_str)); \
ALIGN_DOWN((coal)->item, unit), (obj_str));\
} while (0)
#define CHECK_PKT_RATE_CHANGED(coal, item, ori_val, obj_str) \
do { \
if (coal->item != (ori_val)) \
if ((coal)->item != (ori_val)) \
nicif_info(nic_dev, drv, netdev, \
"Change %s from %llu to %u %s\n", \
#item, (ori_val), coal->item, (obj_str)); \
#item, (ori_val), (coal)->item, (obj_str));\
} while (0)
static int __hinic_set_coalesce(struct net_device *netdev,
......
......@@ -155,7 +155,8 @@ int hinic_aeq_register_swe_cb(void *hwdev, enum hinic_aeq_sw_type event,
void hinic_aeq_unregister_swe_cb(void *hwdev, enum hinic_aeq_sw_type event);
typedef void (*hinic_mgmt_msg_cb)(void *hwdev, void *pri_handle,
u8 cmd, void *buf_in, u16 in_size, void *buf_out, u16 *out_size);
u8 cmd, void *buf_in, u16 in_size,
void *buf_out, u16 *out_size);
int hinic_register_mgmt_msg_cb(void *hwdev,
enum hinic_mod_type mod, void *pri_handle,
......@@ -428,6 +429,7 @@ enum hinic_service_mode {
HINIC_WORK_MODE_NIC,
HINIC_WORK_MODE_INVALID = 0xFF,
};
enum hinic_service_mode hinic_get_service_mode(void *hwdev);
int hinic_slq_init(void *dev, int num_wqs);
......@@ -439,7 +441,8 @@ u64 hinic_slq_get_addr(void *handle, u16 index);
u64 hinic_slq_get_first_pageaddr(void *handle);
typedef void (*comm_up_self_msg_proc)(void *handle, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size);
u16 in_size, void *buf_out,
u16 *out_size);
void hinic_comm_recv_mgmt_self_cmd_reg(void *hwdev, u8 cmd,
comm_up_self_msg_proc proc);
......@@ -753,9 +756,9 @@ int hinic_set_ip_check(void *hwdev, bool ip_check_ctl);
int hinic_mbox_to_host_sync(void *hwdev, enum hinic_mod_type mod,
u8 cmd, void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
int hinic_mbox_ppf_to_vf(void *hwdev,
enum hinic_mod_type mod, u16 func_id, u8 cmd, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size, u32 timeout);
int hinic_mbox_ppf_to_vf(void *hwdev, enum hinic_mod_type mod, u16 func_id,
u8 cmd, void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
int hinic_get_card_present_state(void *hwdev, bool *card_present_state);
......
......@@ -533,6 +533,7 @@ struct hinic_micro_log_info {
int (*init)(void *hwdev);
void (*deinit)(void *hwdev);
};
int hinic_register_micro_log(struct hinic_micro_log_info *micro_log_info);
void hinic_unregister_micro_log(struct hinic_micro_log_info *micro_log_info);
......
......@@ -386,7 +386,7 @@ struct hinic_wq_page_size {
u32 rsvd1;
};
#define MAX_PCIE_DFX_BUF_SIZE (1024)
#define MAX_PCIE_DFX_BUF_SIZE 1024
struct hinic_pcie_dfx_ntc {
u8 status;
......@@ -642,10 +642,11 @@ static void __print_status_info(struct hinic_hwdev *dev,
mod, cmd, mgmt_status_log[index].log);
} else if (mod == HINIC_MOD_L2NIC ||
mod == HINIC_MOD_HILINK) {
if (HINIC_IS_VF(dev) && (cmd == HINIC_PORT_CMD_SET_MAC || cmd ==
HINIC_PORT_CMD_DEL_MAC || cmd ==
HINIC_PORT_CMD_UPDATE_MAC) &&
(mgmt_status_log[index].status == HINIC_PF_SET_VF_ALREADY))
if (HINIC_IS_VF(dev) &&
(cmd == HINIC_PORT_CMD_SET_MAC ||
cmd == HINIC_PORT_CMD_DEL_MAC ||
cmd == HINIC_PORT_CMD_UPDATE_MAC) &&
mgmt_status_log[index].status == HINIC_PF_SET_VF_ALREADY)
return;
nic_err(dev->dev_hdl, "Mgmt process mod(0x%x) cmd(0x%x) fail: %s",
......@@ -694,7 +695,7 @@ static void hinic_print_status_info(void *hwdev, enum hinic_mod_type mod,
if (hinic_status_need_special_handle(mod, cmd, status))
return;
size = sizeof(mgmt_status_log) / sizeof(mgmt_status_log[0]);
size = ARRAY_SIZE(mgmt_status_log);
for (i = 0; i < size; i++) {
if (status == mgmt_status_log[i].status) {
__print_status_info(dev, mod, cmd, i);
......@@ -795,7 +796,8 @@ static int __func_send_mbox(struct hinic_hwdev *hwdev, enum hinic_mod_type mod,
out_size, timeout);
else if (NEED_MBOX_FORWARD(hwdev))
err = hinic_mbox_to_host_sync(hwdev, mod, cmd, buf_in,
in_size, buf_out, out_size, timeout);
in_size, buf_out, out_size,
timeout);
else
err = -EFAULT;
......@@ -1088,8 +1090,7 @@ int hinic_mbox_to_vf(void *hwdev,
EXPORT_SYMBOL(hinic_mbox_to_vf);
int hinic_clp_to_mgmt(void *hwdev, enum hinic_mod_type mod, u8 cmd,
void *buf_in, u16 in_size,
void *buf_out, u16 *out_size)
void *buf_in, u16 in_size, void *buf_out, u16 *out_size)
{
struct hinic_hwdev *dev = hwdev;
......@@ -1958,7 +1959,7 @@ int comm_pf_mbox_handler(void *handle, u16 vf_id, u8 cmd, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size)
{
int err = 0;
u8 size = sizeof(hw_cmd_support_vf) / sizeof(hw_cmd_support_vf[0]);
u8 size = ARRAY_SIZE(hw_cmd_support_vf);
if (!hinic_mbox_check_cmd_valid(handle, hw_cmd_support_vf, vf_id, cmd,
buf_in, in_size, size)) {
......@@ -2173,6 +2174,7 @@ static void hinic_comm_pf_to_mgmt_free(struct hinic_hwdev *hwdev)
hinic_pf_to_mgmt_free(hwdev);
}
static int hinic_comm_clp_to_mgmt_init(struct hinic_hwdev *hwdev)
{
int err;
......@@ -2327,7 +2329,6 @@ static int __get_func_misc_info(struct hinic_hwdev *hwdev)
return 0;
}
/* initialize communication channel */
int hinic_init_comm_ch(struct hinic_hwdev *hwdev)
{
......@@ -3289,7 +3290,7 @@ static struct hinic_event_convert __event_convert[] = {
static enum hinic_event_cmd __get_event_type(u8 mod, u8 cmd)
{
int idx;
int arr_size = sizeof(__event_convert) / sizeof(__event_convert[0]);
int arr_size = ARRAY_SIZE(__event_convert);
for (idx = 0; idx < arr_size; idx++) {
if (__event_convert[idx].mod == mod &&
......@@ -4232,6 +4233,7 @@ static int vf_nic_event_handler(void *hwdev, u8 cmd, void *buf_in,
{
enum hinic_event_cmd type = __get_event_type(HINIC_MOD_L2NIC, cmd);
if (type == HINIC_EVENT_MAX_TYPE) {
sdk_warn(((struct hinic_hwdev *)hwdev)->dev_hdl,
"Unsupport L2NIC event: cmd %d\n", cmd);
......@@ -4249,6 +4251,7 @@ static int vf_comm_event_handler(void *hwdev, u8 cmd, void *buf_in,
{
enum hinic_event_cmd type = __get_event_type(HINIC_MOD_COMM, cmd);
if (type == HINIC_EVENT_MAX_TYPE) {
sdk_warn(((struct hinic_hwdev *)hwdev)->dev_hdl,
"Unsupport COMM event: cmd %d\n", cmd);
......@@ -4267,6 +4270,7 @@ static void pf_nic_event_handler(void *hwdev, void *pri_handle, u8 cmd,
void *buf_out, u16 *out_size)
{
enum hinic_event_cmd type = __get_event_type(HINIC_MOD_L2NIC, cmd);
if (type == HINIC_EVENT_MAX_TYPE) {
sdk_warn(((struct hinic_hwdev *)hwdev)->dev_hdl,
"Unsupport L2NIC event: cmd %d\n", cmd);
......@@ -4282,6 +4286,7 @@ static void pf_hilink_event_handler(void *hwdev, void *pri_handle, u8 cmd,
void *buf_out, u16 *out_size)
{
enum hinic_event_cmd type = __get_event_type(HINIC_MOD_HILINK, cmd);
if (type == HINIC_EVENT_MAX_TYPE) {
sdk_warn(((struct hinic_hwdev *)hwdev)->dev_hdl,
"Unsupport HILINK event: cmd %d\n", cmd);
......
......@@ -354,8 +354,8 @@ int hinic_set_wq_page_size(struct hinic_hwdev *hwdev, u16 func_idx,
int hinic_phy_init_status_judge(void *hwdev);
int hinic_hilink_info_show(struct hinic_hwdev *hwdev);
extern int hinic_api_csr_rd32(void *hwdev, u8 dest, u32 addr, u32 *val);
extern int hinic_api_csr_wr32(void *hwdev, u8 dest, u32 addr, u32 val);
int hinic_api_csr_rd32(void *hwdev, u8 dest, u32 addr, u32 *val);
int hinic_api_csr_wr32(void *hwdev, u8 dest, u32 addr, u32 val);
int hinic_ppf_process_mbox_msg(struct hinic_hwdev *hwdev, u16 pf_idx, u16 vf_id,
enum hinic_mod_type mod, u8 cmd, void *buf_in,
......
......@@ -796,7 +796,6 @@ void hinic_func_own_free(void *hwdev)
hinic_func_own_bit_set(dev, 0);
up(&dev->func_sem);
return;
}
/**
......
......@@ -45,10 +45,10 @@
#define SELF_TEST_BAR_ADDR_OFFSET 0x883c
#define HINIC_SECOND_BASE (1000)
#define HINIC_SYNC_YEAR_OFFSET (1900)
#define HINIC_SYNC_MONTH_OFFSET (1)
#define HINIC_MINUTE_BASE (60)
#define HINIC_SECOND_BASE 1000
#define HINIC_SYNC_YEAR_OFFSET 1900
#define HINIC_SYNC_MONTH_OFFSET 1
#define HINIC_MINUTE_BASE 60
#define HINIC_WAIT_TOOL_CNT_TIMEOUT 10000
#define HINIC_WAIT_SRIOV_CFG_TIMEOUT 15000
......@@ -120,6 +120,7 @@ struct hinic_pcidev {
struct timer_list syncfw_time_timer;
};
#define HINIC_EVENT_PROCESS_TIMEOUT 10000
#define FIND_BIT(num, n) (((num) & (1UL << (n))) ? 1 : 0)
......@@ -261,6 +262,7 @@ static int attach_uld(struct hinic_pcidev *dev, enum hinic_service_type type,
{
void *uld_dev = NULL;
int err;
mutex_lock(&dev->pdev_mutex);
if (dev->init_state < HINIC_INIT_STATE_HWDEV_INITED) {
......@@ -1334,8 +1336,6 @@ void hinic_get_card_func_info_by_card_name(const char *chip_name,
}
lld_dev_put();
return;
}
int hinic_get_device_id(void *hwdev, u16 *dev_id)
......@@ -2187,6 +2187,7 @@ static void hinic_set_vf_load_state(struct hinic_pcidev *pci_adapter,
int hinic_ovs_set_vf_load_state(struct pci_dev *pdev)
{
struct hinic_pcidev *pci_adapter;
if (!pdev) {
pr_err("pdev is null\n");
return -EINVAL;
......@@ -2659,12 +2660,10 @@ static void slave_host_init_delay_work(struct work_struct *work)
clear_bit(HINIC_FUNC_PRB_DELAY, &pci_adapter->flag);
if (err)
set_bit(HINIC_FUNC_PRB_ERR, &pci_adapter->flag);
return;
} else {
queue_delayed_work(pci_adapter->slave_nic_init_workq,
&pci_adapter->slave_nic_init_dwork,
HINIC_SLAVE_NIC_DELAY_TIME);
return;
}
}
......@@ -2861,10 +2860,11 @@ static void __exit hinic_lld_exit(void)
pci_unregister_driver(&hinic_driver);
hinic_unregister_uld(SERVICE_T_NIC);
}
module_init(hinic_lld_init);
module_exit(hinic_lld_exit);
int hinic_register_micro_log(struct hinic_micro_log_info *micro_log_info)
{
struct card_node *chip_node;
......
......@@ -107,12 +107,10 @@ static unsigned char set_link_status_follow = HINIC_LINK_FOLLOW_STATUS_MAX;
module_param(set_link_status_follow, byte, 0444);
MODULE_PARM_DESC(set_link_status_follow, "Set link status follow port status. 0 - default, 1 - follow, 2 - separate, other - unset. (default unset)");
static unsigned int lro_replenish_thld = 256;
module_param(lro_replenish_thld, uint, 0444);
MODULE_PARM_DESC(lro_replenish_thld, "Number wqe for lro replenish buffer (default=256)");
static bool l2nic_interrupt_switch = true;
module_param(l2nic_interrupt_switch, bool, 0644);
MODULE_PARM_DESC(l2nic_interrupt_switch, "Control whether execute l2nic io interrupt switch or not, default is true");
......@@ -2131,14 +2129,14 @@ static void netdev_feature_init(struct net_device *netdev)
}
#define MOD_PARA_VALIDATE_NUM_QPS(nic_dev, num_qps, out_qps) { \
if ((num_qps) > nic_dev->max_qps) \
nic_warn(&nic_dev->pdev->dev, \
if ((num_qps) > (nic_dev)->max_qps) \
nic_warn(&(nic_dev)->pdev->dev, \
"Module Parameter %s value %d is out of range, "\
"Maximum value for the device: %d, using %d\n",\
#num_qps, num_qps, nic_dev->max_qps, \
nic_dev->max_qps); \
if (!(num_qps) || (num_qps) > nic_dev->max_qps) \
out_qps = nic_dev->max_qps; \
#num_qps, num_qps, (nic_dev)->max_qps, \
(nic_dev)->max_qps); \
if (!(num_qps) || (num_qps) > (nic_dev)->max_qps) \
out_qps = (nic_dev)->max_qps; \
else \
out_qps = num_qps; \
}
......@@ -2151,7 +2149,6 @@ static void hinic_try_to_enable_rss(struct hinic_nic_dev *nic_dev)
enum hinic_service_mode service_mode =
hinic_get_service_mode(nic_dev->hwdev);
nic_dev->max_qps = hinic_func_max_nic_qnum(nic_dev->hwdev);
if (nic_dev->max_qps <= 1) {
clear_bit(HINIC_RSS_ENABLE, &nic_dev->flags);
......@@ -2733,7 +2730,6 @@ static int nic_probe(struct hinic_lld_dev *lld_dev, void **uld_dev,
return -ENOMEM;
}
SET_NETDEV_DEV(netdev, &pdev->dev);
nic_dev = (struct hinic_nic_dev *)netdev_priv(netdev);
nic_dev->hwdev = lld_dev->hwdev;
......@@ -2749,7 +2745,6 @@ static int nic_probe(struct hinic_lld_dev *lld_dev, void **uld_dev,
page_num = (RX_BUFF_NUM_PER_PAGE * nic_dev->rx_buff_len) / PAGE_SIZE;
nic_dev->page_order = page_num > 0 ? ilog2(page_num) : 0;
mutex_init(&nic_dev->nic_mutex);
adaptive_configuration_init(nic_dev);
......
......@@ -671,7 +671,7 @@ static bool check_mbox_seq_id_and_seg_len(struct hinic_recv_mbox *recv_mbox,
} else {
if (seq_id != recv_mbox->seq_id + 1)
return false;
else
recv_mbox->seq_id = seq_id;
}
......@@ -1448,9 +1448,9 @@ int __hinic_mbox_to_vf(void *hwdev,
in_size, buf_out, out_size, timeout);
}
int hinic_mbox_ppf_to_vf(void *hwdev,
enum hinic_mod_type mod, u16 func_id, u8 cmd, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size, u32 timeout)
int hinic_mbox_ppf_to_vf(void *hwdev, enum hinic_mod_type mod, u16 func_id,
u8 cmd, void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout)
{
struct hinic_mbox_func_to_func *func_to_func;
int err;
......@@ -1620,7 +1620,8 @@ int hinic_vf_mbox_random_id_init(struct hinic_hwdev *hwdev)
for (vf_in_pf = 1; vf_in_pf <= hinic_func_max_vf(hwdev); vf_in_pf++) {
err = set_vf_mbox_random_id(hwdev,
(hinic_glb_pf_vf_offset(hwdev) + vf_in_pf));
hinic_glb_pf_vf_offset(hwdev) +
vf_in_pf);
if (err)
break;
}
......
......@@ -251,7 +251,8 @@ static void prepare_header(struct hinic_msg_pf_to_mgmt *pf_to_mgmt,
}
static void clp_prepare_header(struct hinic_hwdev *hwdev,
u64 *header, u16 msg_len, enum hinic_mod_type mod,
u64 *header, u16 msg_len,
enum hinic_mod_type mod,
enum hinic_msg_ack_type ack_type,
enum hinic_msg_direction_type direction,
enum hinic_mgmt_cmd cmd, u32 msg_id)
......
......@@ -56,6 +56,7 @@ enum clp_data_type {
HINIC_CLP_REQ_HOST = 0,
HINIC_CLP_RSP_HOST = 1
};
enum clp_reg_type {
HINIC_CLP_BA_HOST = 0,
HINIC_CLP_SIZE_HOST = 1,
......@@ -63,12 +64,13 @@ enum clp_reg_type {
HINIC_CLP_START_REQ_HOST = 3,
HINIC_CLP_READY_RSP_HOST = 4
};
#define HINIC_CLP_REG_GAP (0x20)
#define HINIC_CLP_INPUT_BUFFER_LEN_HOST (4096UL)
#define HINIC_CLP_DATA_UNIT_HOST (4UL)
#define HINIC_BAR01_GLOABAL_CTL_OFFSET (0x4000)
#define HINIC_BAR01_CLP_OFFSET (0x5000)
#define HINIC_CLP_REG_GAP 0x20
#define HINIC_CLP_INPUT_BUFFER_LEN_HOST 4096UL
#define HINIC_CLP_DATA_UNIT_HOST 4UL
#define HINIC_BAR01_GLOABAL_CTL_OFFSET 0x4000
#define HINIC_BAR01_CLP_OFFSET 0x5000
#define HINIC_CLP_SRAM_SIZE_REG (HINIC_BAR01_GLOABAL_CTL_OFFSET + 0x220)
#define HINIC_CLP_REQ_SRAM_BA_REG (HINIC_BAR01_GLOABAL_CTL_OFFSET + 0x224)
......@@ -81,25 +83,25 @@ enum clp_reg_type {
#define HINIC_CLP_RSP_DATA (HINIC_BAR01_CLP_OFFSET + 0x1000)
#define HINIC_CLP_DATA(member) (HINIC_CLP_##member##_DATA)
#define HINIC_CLP_SRAM_SIZE_OFFSET (16)
#define HINIC_CLP_SRAM_BASE_OFFSET (0)
#define HINIC_CLP_LEN_OFFSET (0)
#define HINIC_CLP_START_OFFSET (31)
#define HINIC_CLP_READY_OFFSET (31)
#define HINIC_CLP_SRAM_SIZE_OFFSET 16
#define HINIC_CLP_SRAM_BASE_OFFSET 0
#define HINIC_CLP_LEN_OFFSET 0
#define HINIC_CLP_START_OFFSET 31
#define HINIC_CLP_READY_OFFSET 31
#define HINIC_CLP_OFFSET(member) (HINIC_CLP_##member##_OFFSET)
#define HINIC_CLP_SRAM_SIZE_BIT_LEN (0x7ffUL)
#define HINIC_CLP_SRAM_BASE_BIT_LEN (0x7ffffffUL)
#define HINIC_CLP_LEN_BIT_LEN (0x7ffUL)
#define HINIC_CLP_START_BIT_LEN (0x1UL)
#define HINIC_CLP_READY_BIT_LEN (0x1UL)
#define HINIC_CLP_SRAM_SIZE_BIT_LEN 0x7ffUL
#define HINIC_CLP_SRAM_BASE_BIT_LEN 0x7ffffffUL
#define HINIC_CLP_LEN_BIT_LEN 0x7ffUL
#define HINIC_CLP_START_BIT_LEN 0x1UL
#define HINIC_CLP_READY_BIT_LEN 0x1UL
#define HINIC_CLP_MASK(member) (HINIC_CLP_##member##_BIT_LEN)
#define HINIC_CLP_DELAY_CNT_MAX (200UL)
#define HINIC_CLP_SRAM_SIZE_REG_MAX (0x3ff)
#define HINIC_CLP_SRAM_BASE_REG_MAX (0x7ffffff)
#define HINIC_CLP_LEN_REG_MAX (0x3ff)
#define HINIC_CLP_START_OR_READY_REG_MAX (0x1)
#define HINIC_CLP_DELAY_CNT_MAX 200UL
#define HINIC_CLP_SRAM_SIZE_REG_MAX 0x3ff
#define HINIC_CLP_SRAM_BASE_REG_MAX 0x7ffffff
#define HINIC_CLP_LEN_REG_MAX 0x3ff
#define HINIC_CLP_START_OR_READY_REG_MAX 0x1
enum hinic_msg_direction_type {
HINIC_MSG_DIRECT_SEND = 0,
......
......@@ -939,10 +939,12 @@ struct hinic_link_ksettings_info {
u8 fec; /* 0 - RSFEC; 1 - BASEFEC; 2 - NOFEC */
u8 rsvd2[18]; /* reserved for duplex, port, etc. */
};
enum hinic_tx_promsic {
HINIC_TX_PROMISC_ENABLE = 0,
HINIC_TX_PROMISC_DISABLE = 1,
};
struct hinic_promsic_info {
u8 status;
u8 version;
......
......@@ -450,7 +450,8 @@ static int multi_host_event_handler(struct hinic_hwdev *hwdev,
}
static int sw_fwd_msg_to_vf(struct hinic_hwdev *hwdev,
void *buf_in, u16 in_size, void *buf_out, u16 *out_size)
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size)
{
struct hinic_host_fwd_head *fwd_head;
u16 fwd_head_len;
......@@ -462,7 +463,7 @@ static int sw_fwd_msg_to_vf(struct hinic_hwdev *hwdev,
msg = (void *)((u8 *)buf_in + fwd_head_len);
err = hinic_mbox_ppf_to_vf(hwdev, fwd_head->mod,
fwd_head->dst_glb_func_idx, fwd_head->cmd,
msg, (in_size - fwd_head_len),
msg, in_size - fwd_head_len,
buf_out, out_size, 0);
if (err)
nic_err(hwdev->dev_hdl,
......@@ -471,6 +472,7 @@ static int sw_fwd_msg_to_vf(struct hinic_hwdev *hwdev,
return err;
}
static int __slave_host_sw_func_handler(struct hinic_hwdev *hwdev, u16 pf_idx,
u8 cmd, void *buf_in, u16 in_size,
void *buf_out, u16 *out_size)
......@@ -550,7 +552,8 @@ int __ppf_process_mbox_msg(struct hinic_hwdev *hwdev, u16 pf_idx, u16 vf_id,
if (IS_SLAVE_HOST(hwdev)) {
err = hinic_mbox_to_host_sync(hwdev, mod, cmd,
buf_in, in_size, buf_out, out_size, 0);
buf_in, in_size, buf_out,
out_size, 0);
if (err)
sdk_err(hwdev->dev_hdl, "send to mpf failed, err: %d\n",
err);
......
......@@ -2584,7 +2584,7 @@ static void hinic_get_vf_cos_msg_handler(struct hinic_nic_io *nic_io,
int nic_pf_mbox_handler(void *hwdev, u16 vf_id, u8 cmd, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size)
{
u8 size = sizeof(nic_cmd_support_vf) / sizeof(nic_cmd_support_vf[0]);
u8 size = ARRAY_SIZE(nic_cmd_support_vf);
struct hinic_nic_io *nic_io;
int err = 0;
u32 timeout = 0;
......@@ -3819,6 +3819,7 @@ int hinic_set_link_settings(void *hwdev, struct hinic_link_ksettings *settings)
return info.status;
}
int hinic_disable_tx_promisc(void *hwdev)
{
struct hinic_promsic_info info = {0};
......
......@@ -31,7 +31,7 @@
#include "hinic_nic.h"
#include "hinic_dbg.h"
#define INVALID_PI (0xFFFF)
#define INVALID_PI 0xFFFF
u16 hinic_dbg_get_qp_num(void *hwdev)
{
......
......@@ -136,9 +136,9 @@ struct hinic_intr_coal_info {
#define HINIC_NIC_STATS_INC(nic_dev, field) \
{ \
u64_stats_update_begin(&nic_dev->stats.syncp); \
nic_dev->stats.field++; \
u64_stats_update_end(&nic_dev->stats.syncp); \
u64_stats_update_begin(&(nic_dev)->stats.syncp); \
(nic_dev)->stats.field++; \
u64_stats_update_end(&(nic_dev)->stats.syncp); \
}
struct hinic_nic_stats {
......@@ -268,12 +268,12 @@ int hinic_enable_func_rss(struct hinic_nic_dev *nic_dev);
#define hinic_msg(level, nic_dev, msglvl, format, arg...) \
do { \
if (nic_dev->netdev && nic_dev->netdev->reg_state \
if ((nic_dev)->netdev && (nic_dev)->netdev->reg_state \
== NETREG_REGISTERED) \
nicif_##level(nic_dev, msglvl, nic_dev->netdev, \
nicif_##level((nic_dev), msglvl, (nic_dev)->netdev, \
format, ## arg); \
else \
nic_##level(&nic_dev->pdev->dev, \
nic_##level(&(nic_dev)->pdev->dev, \
format, ## arg); \
} while (0)
......
......@@ -997,6 +997,7 @@ static int get_homologue(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
{
struct hinic_homologues *homo = buf_out;
if (!buf_out || *out_size != sizeof(*homo)) {
nicif_err(nic_dev, drv, nic_dev->netdev,
"Unexpect out buf size from user: %d, expect: %lu\n",
......@@ -1018,6 +1019,7 @@ static int set_homologue(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
{
struct hinic_homologues *homo = buf_in;
if (!buf_in || in_size != sizeof(*homo)) {
nicif_err(nic_dev, drv, nic_dev->netdev,
"Unexpect in buf size from user: %d, expect: %lu\n",
......@@ -1228,6 +1230,7 @@ static int get_device_id(void *hwdev, void *buf_in, u32 in_size,
{
u16 dev_id;
int err;
if (!buf_out || !buf_in || *out_size != sizeof(u16) ||
in_size != sizeof(u16)) {
pr_err("Unexpect out buf size from user: %d, expect: %lu\n",
......
......@@ -50,11 +50,11 @@ struct ipsurx_stats_info {
struct ucode_cmd_st {
union {
struct {
u32 comm_mod_type:8;
u32 ucode_cmd_type:4;
u32 cmdq_ack_type:3;
u32 ucode_imm:1;
u32 len:16;
u32 comm_mod_type : 8;
u32 ucode_cmd_type : 4;
u32 cmdq_ack_type : 3;
u32 ucode_imm : 1;
u32 len : 16;
} ucode_db;
u32 value;
};
......@@ -63,9 +63,9 @@ struct ucode_cmd_st {
struct up_cmd_st {
union {
struct {
u32 comm_mod_type:8;
u32 chipif_cmd:8;
u32 up_api_type:16;
u32 comm_mod_type : 8;
u32 chipif_cmd : 8;
u32 up_api_type : 16;
} up_db;
u32 value;
};
......@@ -97,11 +97,11 @@ union _pfc {
union _flag_com {
struct _ets_flag {
u8 flag_ets_enable:1;
u8 flag_ets_percent:1;
u8 flag_ets_cos:1;
u8 flag_ets_strict:1;
u8 rev:4;
u8 flag_ets_enable : 1;
u8 flag_ets_percent : 1;
u8 flag_ets_cos : 1;
u8 flag_ets_strict : 1;
u8 rev : 4;
} ets_flag;
u8 data;
};
......@@ -166,8 +166,8 @@ struct hinic_tx_hw_page {
struct hinic_dbg_sq_info {
u16 q_id;
u16 pi;
u16 ci;/* sw_ci */
u16 fi;/* hw_ci */
u16 ci; /* sw_ci */
u16 fi; /* hw_ci */
u32 q_depth;
u16 pi_reverse;
......@@ -268,8 +268,8 @@ struct hinic_pf_info {
int nictool_k_init(void);
void nictool_k_uninit(void);
extern u32 hinic_get_io_stats_size(struct hinic_nic_dev *nic_dev);
extern void hinic_get_io_stats(struct hinic_nic_dev *nic_dev,
u32 hinic_get_io_stats_size(struct hinic_nic_dev *nic_dev);
void hinic_get_io_stats(struct hinic_nic_dev *nic_dev,
struct hinic_show_item *items);
#define TOOL_COUNTER_MAX_LEN 512
......
......@@ -518,7 +518,7 @@ enum hinic_doorbell_ctrl {
};
enum hinic_pf_status {
HINIC_PF_STATUS_INIT = 0X0,
HINIC_PF_STATUS_INIT = 0x0,
HINIC_PF_STATUS_ACTIVE_FLAG = 0x11,
HINIC_PF_STATUS_FLR_START_FLAG = 0x12,
HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,
......
......@@ -160,8 +160,8 @@
#define SQ_DB_INFO_CFLAG_MASK 0x1U
#define SQ_DB_INFO_COS_MASK 0x7U
#define SQ_DB_INFO_TYPE_MASK 0x1FU
#define SQ_DB_INFO_SET(val, member) (((u32)(val) & \
SQ_DB_INFO_##member##_MASK) << \
#define SQ_DB_INFO_SET(val, member) \
(((u32)(val) & SQ_DB_INFO_##member##_MASK) << \
SQ_DB_INFO_##member##_SHIFT)
#define SQ_DB_PI_LOW_MASK 0xFF
......@@ -184,16 +184,16 @@
#define RQ_CTRL_COMPLETE_LEN_MASK 0x3U
#define RQ_CTRL_LEN_MASK 0x3U
#define RQ_CTRL_SET(val, member) (((val) & \
RQ_CTRL_##member##_MASK) << \
#define RQ_CTRL_SET(val, member) \
(((val) & RQ_CTRL_##member##_MASK) << \
RQ_CTRL_##member##_SHIFT)
#define RQ_CTRL_GET(val, member) (((val) >> \
RQ_CTRL_##member##_SHIFT) & \
#define RQ_CTRL_GET(val, member) \
(((val) >> RQ_CTRL_##member##_SHIFT) & \
RQ_CTRL_##member##_MASK)
#define RQ_CTRL_CLEAR(val, member) ((val) & \
(~(RQ_CTRL_##member##_MASK << \
#define RQ_CTRL_CLEAR(val, member) \
((val) & (~(RQ_CTRL_##member##_MASK << \
RQ_CTRL_##member##_SHIFT)))
#define RQ_CQE_STATUS_CSUM_ERR_SHIFT 0
......@@ -215,12 +215,12 @@
#define RQ_CQE_STATUS_RXDONE_MASK 0x1U
#define RQ_CQE_STATUS_FLUSH_MASK 0x1U
#define RQ_CQE_STATUS_GET(val, member) (((val) >> \
RQ_CQE_STATUS_##member##_SHIFT) & \
#define RQ_CQE_STATUS_GET(val, member) \
(((val) >> RQ_CQE_STATUS_##member##_SHIFT) & \
RQ_CQE_STATUS_##member##_MASK)
#define RQ_CQE_STATUS_CLEAR(val, member) ((val) & \
(~(RQ_CQE_STATUS_##member##_MASK << \
#define RQ_CQE_STATUS_CLEAR(val, member) \
((val) & (~(RQ_CQE_STATUS_##member##_MASK << \
RQ_CQE_STATUS_##member##_SHIFT)))
#define RQ_CQE_SGE_VLAN_SHIFT 0
......@@ -229,8 +229,8 @@
#define RQ_CQE_SGE_VLAN_MASK 0xFFFFU
#define RQ_CQE_SGE_LEN_MASK 0xFFFFU
#define RQ_CQE_SGE_GET(val, member) (((val) >> \
RQ_CQE_SGE_##member##_SHIFT) & \
#define RQ_CQE_SGE_GET(val, member) \
(((val) >> RQ_CQE_SGE_##member##_SHIFT) & \
RQ_CQE_SGE_##member##_MASK)
#define RQ_CQE_PKT_NUM_SHIFT 1
......@@ -243,20 +243,20 @@
#define RQ_CQE_PKT_NUM_MASK 0x1FU
#define RQ_CQE_SUPER_CQE_EN_MASK 0x1
#define RQ_CQE_PKT_NUM_GET(val, member) (((val) >> \
RQ_CQE_PKT_##member##_SHIFT) & \
#define RQ_CQE_PKT_NUM_GET(val, member) \
(((val) >> RQ_CQE_PKT_##member##_SHIFT) & \
RQ_CQE_PKT_##member##_MASK)
#define HINIC_GET_RQ_CQE_PKT_NUM(pkt_info) RQ_CQE_PKT_NUM_GET(pkt_info, NUM)
#define RQ_CQE_SUPER_CQE_EN_GET(val, member) (((val) >> \
RQ_CQE_##member##_SHIFT) & \
#define RQ_CQE_SUPER_CQE_EN_GET(val, member) \
(((val) >> RQ_CQE_##member##_SHIFT) & \
RQ_CQE_##member##_MASK)
#define HINIC_GET_SUPER_CQE_EN(pkt_info) \
RQ_CQE_SUPER_CQE_EN_GET(pkt_info, SUPER_CQE_EN)
#define HINIC_GET_SUPER_CQE_EN_BE(pkt_info) ((pkt_info) & 0x1000000U)
#define RQ_CQE_PKT_LEN_GET(val, member) (((val) >> \
RQ_CQE_PKT_##member##_SHIFT) & \
#define RQ_CQE_PKT_LEN_GET(val, member) \
(((val) >> RQ_CQE_PKT_##member##_SHIFT) & \
RQ_CQE_PKT_##member##_MASK)
#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_SHIFT 21
......@@ -271,8 +271,8 @@
#define RQ_CQE_OFFOLAD_TYPE_RSS_TYPE_SHIFT 24
#define RQ_CQE_OFFOLAD_TYPE_RSS_TYPE_MASK 0xFFU
#define RQ_CQE_OFFOLAD_TYPE_GET(val, member) (((val) >> \
RQ_CQE_OFFOLAD_TYPE_##member##_SHIFT) & \
#define RQ_CQE_OFFOLAD_TYPE_GET(val, member) \
(((val) >> RQ_CQE_OFFOLAD_TYPE_##member##_SHIFT) & \
RQ_CQE_OFFOLAD_TYPE_##member##_MASK)
#define RQ_CQE_PKT_TYPES_NON_L2_MASK 0x800U
......@@ -434,16 +434,16 @@ enum hinic_res_state {
((pkt_types) & RQ_CQE_PKT_TYPES_NON_L2_MASK)
#define HINIC_PKT_TYPES_L2(pkt_types) \
(pkt_types & RQ_CQE_PKT_TYPES_L2_MASK)
((pkt_types) & RQ_CQE_PKT_TYPES_L2_MASK)
#define HINIC_CSUM_ERR_BYPASSED(csum_err) \
(csum_err == RQ_CQE_STATUS_CSUM_BYPASS_VAL)
((csum_err) == RQ_CQE_STATUS_CSUM_BYPASS_VAL)
#define HINIC_CSUM_ERR_IP(csum_err) \
(csum_err & RQ_CQE_STATUS_CSUM_ERR_IP_MASK)
((csum_err) & RQ_CQE_STATUS_CSUM_ERR_IP_MASK)
#define HINIC_CSUM_ERR_L4(csum_err) \
(csum_err & RQ_CQE_STATUS_CSUM_ERR_L4_MASK)
((csum_err) & RQ_CQE_STATUS_CSUM_ERR_L4_MASK)
#define TX_MSS_DEFAULT 0x3E00
#define TX_MSS_MIN 0x50
......
......@@ -48,9 +48,9 @@ static void hinic_clear_rss_config_user(struct hinic_nic_dev *nic_dev);
#define RXQ_STATS_INC(rxq, field) \
{ \
u64_stats_update_begin(&rxq->rxq_stats.syncp); \
rxq->rxq_stats.field++; \
u64_stats_update_end(&rxq->rxq_stats.syncp); \
u64_stats_update_begin(&(rxq)->rxq_stats.syncp); \
(rxq)->rxq_stats.field++; \
u64_stats_update_end(&(rxq)->rxq_stats.syncp); \
}
static bool rx_alloc_mapped_page(struct hinic_rxq *rxq,
......
......@@ -16,8 +16,8 @@
#ifndef __CHIPIF_SM_LT_H__
#define __CHIPIF_SM_LT_H__
#define SM_LT_LOAD (0x12)
#define SM_LT_STORE (0x14)
#define SM_LT_LOAD 0x12
#define SM_LT_STORE 0x14
#define SM_LT_NUM_OFFSET 13
#define SM_LT_ABUF_FLG_OFFSET 12
......@@ -52,15 +52,15 @@ enum {
/* lt load request */
typedef union {
struct {
u32 offset:8;
u32 pad:3;
u32 bc:1;
u32 abuf_flg:1;
u32 num:2;
u32 ack:1;
u32 op_id:5;
u32 instance:6;
u32 src:5;
u32 offset : 8;
u32 pad : 3;
u32 bc : 1;
u32 abuf_flg : 1;
u32 num : 2;
u32 ack : 1;
u32 op_id : 5;
u32 instance : 6;
u32 src : 5;
} bs;
u32 value;
......@@ -178,30 +178,30 @@ struct hinic_csr_request_api_data {
union {
struct {
u32 reserved1:13;
u32 reserved1 : 13;
/* this field indicates the write/read data size:
* 2'b00: 32 bits
* 2'b01: 64 bits
* 2'b10~2'b11:reserved
*/
u32 data_size:2;
u32 data_size : 2;
/* this field indicates that requestor expect receive a
* response data or not.
* 1'b0: expect not to receive a response data.
* 1'b1: expect to receive a response data.
*/
u32 need_response:1;
u32 need_response : 1;
/* this field indicates the operation that the requestor
* expected.
* 5'b1_1110: write value to csr space.
* 5'b1_1111: read register from csr space.
*/
u32 operation_id:5;
u32 reserved2:6;
u32 operation_id : 5;
u32 reserved2 : 6;
/* this field specifies the Src node ID for this API
* request message.
*/
u32 src_node_id:5;
u32 src_node_id : 5;
} bits;
u32 val32;
......@@ -210,8 +210,8 @@ struct hinic_csr_request_api_data {
union {
struct {
/* it specifies the CSR address. */
u32 csr_addr:26;
u32 reserved3:6;
u32 csr_addr : 26;
u32 reserved3 : 6;
} bits;
u32 val32;
......
......@@ -32,11 +32,11 @@
/* request head */
typedef union {
struct {
u32 pad:15;
u32 ack:1;
u32 op_id:5;
u32 instance:6;
u32 src:5;
u32 pad : 15;
u32 ack : 1;
u32 op_id : 5;
u32 instance : 6;
u32 src : 5;
} bs;
u32 value;
......@@ -53,8 +53,8 @@ typedef struct {
/* counter read response union */
typedef union {
struct {
u32 value1:16;
u32 pad0:16;
u32 value1 : 16;
u32 pad0 : 16;
u32 pad1[3];
} bs_ss16_rsp;
......@@ -64,10 +64,10 @@ typedef union {
} bs_ss32_rsp;
struct {
u32 value1:20;
u32 pad0:12;
u32 value2:12;
u32 pad1:20;
u32 value1 : 20;
u32 pad0 : 12;
u32 value2 : 12;
u32 pad1 : 20;
u32 pad2[2];
} bs_sp_rsp;
......@@ -89,8 +89,8 @@ typedef union {
/* resopnse head */
typedef union {
struct {
u32 pad:30; /* reserve */
u32 code:2; /* error code */
u32 pad : 30; /* reserve */
u32 code : 2; /* error code */
} bs;
u32 value;
......
......@@ -48,9 +48,9 @@
#define TXQ_STATS_INC(txq, field) \
{ \
u64_stats_update_begin(&txq->txq_stats.syncp); \
txq->txq_stats.field++; \
u64_stats_update_end(&txq->txq_stats.syncp); \
u64_stats_update_begin(&(txq)->txq_stats.syncp); \
(txq)->txq_stats.field++; \
u64_stats_update_end(&(txq)->txq_stats.syncp); \
}
void hinic_txq_get_stats(struct hinic_txq *txq,
......@@ -287,6 +287,7 @@ static void get_inner_l3_l4_type(struct sk_buff *skb, union hinic_ip *ip,
*l4_proto = ip->v6->nexthdr;
if (exthdr != l4->hdr) {
__be16 frag_off = 0;
ipv6_skip_exthdr(skb, (int)(exthdr - skb->data),
l4_proto, &frag_off);
}
......
......@@ -19,21 +19,21 @@
#include "ossl_knl_linux.h"
#define sdk_err(dev, format, ...) \
dev_err(dev, "[COMM]"format, ##__VA_ARGS__)
dev_err(dev, "[COMM]" format, ##__VA_ARGS__)
#define sdk_warn(dev, format, ...) \
dev_warn(dev, "[COMM]"format, ##__VA_ARGS__)
dev_warn(dev, "[COMM]" format, ##__VA_ARGS__)
#define sdk_notice(dev, format, ...) \
dev_notice(dev, "[COMM]"format, ##__VA_ARGS__)
dev_notice(dev, "[COMM]" format, ##__VA_ARGS__)
#define sdk_info(dev, format, ...) \
dev_info(dev, "[COMM]"format, ##__VA_ARGS__)
dev_info(dev, "[COMM]" format, ##__VA_ARGS__)
#define nic_err(dev, format, ...) \
dev_err(dev, "[NIC]"format, ##__VA_ARGS__)
dev_err(dev, "[NIC]" format, ##__VA_ARGS__)
#define nic_warn(dev, format, ...) \
dev_warn(dev, "[NIC]"format, ##__VA_ARGS__)
dev_warn(dev, "[NIC]" format, ##__VA_ARGS__)
#define nic_notice(dev, format, ...) \
dev_notice(dev, "[NIC]"format, ##__VA_ARGS__)
dev_notice(dev, "[NIC]" format, ##__VA_ARGS__)
#define nic_info(dev, format, ...) \
dev_info(dev, "[NIC]"format, ##__VA_ARGS__)
dev_info(dev, "[NIC]" format, ##__VA_ARGS__)
#endif /* OSSL_KNL_H */
......@@ -59,15 +59,15 @@
int local_atoi(const char *name);
#define nicif_err(priv, type, dev, fmt, args...) \
netif_level(err, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(err, priv, type, dev, "[NIC]" fmt, ##args)
#define nicif_warn(priv, type, dev, fmt, args...) \
netif_level(warn, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(warn, priv, type, dev, "[NIC]" fmt, ##args)
#define nicif_notice(priv, type, dev, fmt, args...) \
netif_level(notice, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(notice, priv, type, dev, "[NIC]" fmt, ##args)
#define nicif_info(priv, type, dev, fmt, args...) \
netif_level(info, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(info, priv, type, dev, "[NIC]" fmt, ##args)
#define nicif_dbg(priv, type, dev, fmt, args...) \
netif_level(dbg, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(dbg, priv, type, dev, "[NIC]" fmt, ##args)
#define tasklet_state(tasklet) ((tasklet)->state)
......
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