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提交 e6a07712 编写于 作者: C Chiqijun 提交者： Yang Yingliang
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net/hinic: Fix alignment and code style 

driver inclusion
category: bugfix
bugzilla: 4472

-----------------------------------------------------------------------

Fix alignment and code style.
Signed-off-by: NChiqijun <chiqijun@huawei.com>
Reviewed-by: NZengweiliang <zengweiliang.zengweiliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 0389e4b3
隐藏空白更改
内联 并排
Showing with 690 addition and 672 deletion
drivers/net/ethernet/huawei/hinic/hinic_api_cmd.c
浏览文件 @ e6a07712
......@@ -203,9 +203,9 @@ static u16 get_cell_data_size(enum hinic_api_cmd_chain_type type, u16 cmd_size)
switch (type) {
case HINIC_API_CMD_POLL_READ:
cell_data_size = ALIGN(API_CMD_CELL_DESC_SIZE +
API_CMD_CELL_WB_ADDR_SIZE +
API_CMD_CELL_DATA_ADDR_SIZE,
API_CHAIN_CELL_ALIGNMENT);
API_CMD_CELL_WB_ADDR_SIZE +
API_CMD_CELL_DATA_ADDR_SIZE,
API_CHAIN_CELL_ALIGNMENT);
break;
case HINIC_API_CMD_WRITE_TO_MGMT_CPU:
......@@ -253,9 +253,9 @@ static void prepare_cell_ctrl(u64 *cell_ctrl, u16 cell_len)
* @cmd_size: the command size
*/
static void prepare_api_cmd(struct hinic_api_cmd_chain *chain,
struct hinic_api_cmd_cell *cell,
enum hinic_node_id dest,
const void *cmd, u16 cmd_size)
struct hinic_api_cmd_cell *cell,
enum hinic_node_id dest,
const void *cmd, u16 cmd_size)
{
struct hinic_api_cmd_cell_ctxt *cell_ctxt;
u32 priv;
......@@ -299,7 +299,7 @@ static void prepare_api_cmd(struct hinic_api_cmd_chain *chain,
HINIC_API_CMD_DESC_SET(SIZE_4BYTES(cmd_size), SIZE);
cell->desc |= HINIC_API_CMD_DESC_SET(xor_chksum_set(&cell->desc),
XOR_CHKSUM);
XOR_CHKSUM);
/* The data in the HW should be in Big Endian Format */
cell->desc = cpu_to_be64(cell->desc);
......@@ -559,7 +559,7 @@ int hinic_api_cmd_write(struct hinic_api_cmd_chain *chain,
int hinic_api_cmd_read(struct hinic_api_cmd_chain *chain,
enum hinic_node_id dest,
void *cmd, u16 size, void *ack, u16 ack_size)
void *cmd, u16 size, void *ack, u16 ack_size)
{
return api_cmd(chain, dest, cmd, size, ack, ack_size);
}
......
drivers/net/ethernet/huawei/hinic/hinic_api_cmd.h
浏览文件 @ e6a07712
......@@ -52,7 +52,7 @@
((((u64)val) & HINIC_API_CMD_DESC_##member##_MASK) << \
HINIC_API_CMD_DESC_##member##_SHIFT)
#define HINIC_API_CMD_STATUS_HEADER_VALID_SHIFT 0
#define HINIC_API_CMD_STATUS_HEADER_VALID_SHIFT 0
#define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_SHIFT 16
#define HINIC_API_CMD_STATUS_HEADER_VALID_MASK 0xFFU
......@@ -109,7 +109,7 @@
#define HINIC_API_CMD_RESP_HEADER_VALID(val) \
(((val) & HINIC_API_CMD_RESP_HEAD_VALID_MASK) == \
HINIC_API_CMD_RESP_HEAD_VALID_CODE)
HINIC_API_CMD_RESP_HEAD_VALID_CODE)
#define HINIC_API_CMD_RESP_HEAD_STATUS_SHIFT 8
#define HINIC_API_CMD_RESP_HEAD_STATUS_MASK 0xFFU
......@@ -117,8 +117,8 @@
#define HINIC_API_CMD_RESP_HEAD_ERR_CODE 0x1
#define HINIC_API_CMD_RESP_HEAD_ERR(val) \
((((val) >> HINIC_API_CMD_RESP_HEAD_STATUS_SHIFT) & \
HINIC_API_CMD_RESP_HEAD_STATUS_MASK) == \
HINIC_API_CMD_RESP_HEAD_ERR_CODE)
HINIC_API_CMD_RESP_HEAD_STATUS_MASK) == \
HINIC_API_CMD_RESP_HEAD_ERR_CODE)
#define HINIC_API_CMD_RESP_HEAD_CHAIN_ID_SHIFT 16
#define HINIC_API_CMD_RESP_HEAD_CHAIN_ID_MASK 0xFF
......@@ -126,19 +126,19 @@
#define HINIC_API_CMD_RESP_RESERVED 3
#define HINIC_API_CMD_RESP_HEAD_CHAIN_ID(val) \
(((val) >> HINIC_API_CMD_RESP_HEAD_CHAIN_ID_SHIFT) & \
HINIC_API_CMD_RESP_HEAD_CHAIN_ID_MASK)
HINIC_API_CMD_RESP_HEAD_CHAIN_ID_MASK)
#define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_SHIFT 40
#define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK 0xFFFFFFU
#define HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV(val) \
(u16)(((val) >> HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_SHIFT) & \
HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK)
HINIC_API_CMD_RESP_HEAD_DRIVER_PRIV_MASK)
#define HINIC_API_CMD_STATUS_HEAD_VALID_MASK 0xFFU
#define HINIC_API_CMD_STATUS_HEAD_VALID_SHIFT 0
#define HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_MASK 0xFFU
#define HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_MASK 0xFFU
#define HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_VALID_SHIFT 16
#define HINIC_API_CMD_STATUS_CONS_IDX_MASK 0xFFFFFFU
......@@ -155,18 +155,18 @@
#define HINIC_API_CMD_STATUS_CHAIN_ID(val) \
(((val) >> HINIC_API_CMD_STATUS_HEAD_CHAIN_ID_VALID_SHIFT) & \
HINIC_API_CMD_STATUS_HEAD_VALID_MASK)
HINIC_API_CMD_STATUS_HEAD_VALID_MASK)
#define HINIC_API_CMD_STATUS_CONS_IDX(val) \
((val) & HINIC_API_CMD_STATUS_CONS_IDX_MASK)
#define HINIC_API_CMD_STATUS_CHKSUM_ERR(val) \
(((val) >> HINIC_API_CMD_STATUS_CHKSUM_ERR_SHIFT) & \
HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK)
HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK)
#define HINIC_API_CMD_STATUS_GET(val, member) \
(((val) >> HINIC_API_CMD_STATUS_##member##_SHIFT) & \
HINIC_API_CMD_STATUS_##member##_MASK)
HINIC_API_CMD_STATUS_##member##_MASK)
enum hinic_api_cmd_chain_type {
/* write command with completion notification */
......
drivers/net/ethernet/huawei/hinic/hinic_cfg.c
浏览文件 @ e6a07712
......@@ -561,7 +561,6 @@ static void parse_dev_cap(struct hinic_hwdev *dev,
if (IS_NIC_TYPE(dev))
parse_l2nic_res_cap(dev, cap, dev_cap, type);
/* FCoE/IOE/TOE/FC without virtulization */
if (type == TYPE_PF || type == TYPE_PPF) {
if (IS_FC_TYPE(dev))
......@@ -677,7 +676,6 @@ static void nic_param_fix(struct hinic_hwdev *dev)
nic_cap->max_rqs = nic_cap->max_queue_allowed;
nic_cap->max_sqs = nic_cap->max_queue_allowed;
}
}
static void rdma_param_fix(struct hinic_hwdev *dev)
......@@ -1207,7 +1205,7 @@ int hinic_alloc_ceqs(void *hwdev, enum hinic_service_type type, int num,
for (i = 0; i < num; i++) {
if (eq->num_ceq_remain == 0) {
sdk_warn(dev->dev_hdl, "Alloc %d ceqs, less than required %d ceqs\n",
*act_num, num);
*act_num, num);
mutex_unlock(&eq->eq_mutex);
return 0;
}
......@@ -1385,8 +1383,8 @@ static int cfg_mbx_pf_proc_vf_msg(void *hwdev, u16 vf_id, u8 cmd, void *buf_in,
}
static int cfg_mbx_ppf_proc_msg(void *hwdev, u16 pf_id, u16 vf_id, u8 cmd,
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size)
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size)
{
struct hinic_hwdev *dev = hwdev;
......@@ -1399,7 +1397,7 @@ static int cfg_mbx_ppf_proc_msg(void *hwdev, u16 pf_id, u16 vf_id, u8 cmd,
}
static int cfg_mbx_vf_proc_msg(void *hwdev, u8 cmd, void *buf_in, u16 in_size,
void *buf_out, u16 *out_size)
void *buf_out, u16 *out_size)
{
struct hinic_hwdev *dev = hwdev;
......@@ -1546,8 +1544,8 @@ void free_cfg_mgmt(struct hinic_hwdev *dev)
int init_capability(struct hinic_hwdev *dev)
{
int err;
struct cfg_mgmt_info *cfg_mgmt = dev->cfg_mgmt;
int err;
set_cfg_test_param(cfg_mgmt);
......@@ -2153,6 +2151,7 @@ static void hinic_os_dep_deinit(struct hinic_hwdev *hwdev)
void hinic_ppf_hwdev_unreg(void *hwdev)
{
struct hinic_hwdev *dev = hwdev;
if (!hwdev)
return;
......@@ -2166,6 +2165,7 @@ void hinic_ppf_hwdev_unreg(void *hwdev)
void hinic_ppf_hwdev_reg(void *hwdev, void *ppf_hwdev)
{
struct hinic_hwdev *dev = hwdev;
if (!hwdev)
return;
......
drivers/net/ethernet/huawei/hinic/hinic_cmdq.c
浏览文件 @ e6a07712
......@@ -54,8 +54,8 @@
#define CMDQ_DB_INFO_SRC_TYPE_MASK 0x1FU
#define CMDQ_DB_INFO_SET(val, member) \
((val & CMDQ_DB_INFO_##member##_MASK) \
<< CMDQ_DB_INFO_##member##_SHIFT)
(((val) & CMDQ_DB_INFO_##member##_MASK) \
<< CMDQ_DB_INFO_##member##_SHIFT)
#define CMDQ_CTRL_PI_SHIFT 0
#define CMDQ_CTRL_CMD_SHIFT 16
......@@ -71,11 +71,11 @@
#define CMDQ_CTRL_SET(val, member) \
(((val) & CMDQ_CTRL_##member##_MASK) \
<< CMDQ_CTRL_##member##_SHIFT)
<< CMDQ_CTRL_##member##_SHIFT)
#define CMDQ_CTRL_GET(val, member) \
(((val) >> CMDQ_CTRL_##member##_SHIFT) \
& CMDQ_CTRL_##member##_MASK)
& CMDQ_CTRL_##member##_MASK)
#define CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT 0
#define CMDQ_WQE_HEADER_COMPLETE_FMT_SHIFT 15
......@@ -95,69 +95,69 @@
#define CMDQ_WQE_HEADER_SET(val, member) \
(((val) & CMDQ_WQE_HEADER_##member##_MASK) \
<< CMDQ_WQE_HEADER_##member##_SHIFT)
<< CMDQ_WQE_HEADER_##member##_SHIFT)
#define CMDQ_WQE_HEADER_GET(val, member) \
(((val) >> CMDQ_WQE_HEADER_##member##_SHIFT) \
& CMDQ_WQE_HEADER_##member##_MASK)
& CMDQ_WQE_HEADER_##member##_MASK)
#define CMDQ_CTXT_CURR_WQE_PAGE_PFN_SHIFT 0
#define CMDQ_CTXT_EQ_ID_SHIFT 56
#define CMDQ_CTXT_CEQ_ARM_SHIFT 61
#define CMDQ_CTXT_CEQ_EN_SHIFT 62
#define CMDQ_CTXT_HW_BUSY_BIT_SHIFT 63
#define CMDQ_CTXT_CURR_WQE_PAGE_PFN_SHIFT 0
#define CMDQ_CTXT_EQ_ID_SHIFT 56
#define CMDQ_CTXT_CEQ_ARM_SHIFT 61
#define CMDQ_CTXT_CEQ_EN_SHIFT 62
#define CMDQ_CTXT_HW_BUSY_BIT_SHIFT 63
#define CMDQ_CTXT_CURR_WQE_PAGE_PFN_MASK 0xFFFFFFFFFFFFF
#define CMDQ_CTXT_EQ_ID_MASK 0x1F
#define CMDQ_CTXT_CEQ_ARM_MASK 0x1
#define CMDQ_CTXT_CEQ_EN_MASK 0x1
#define CMDQ_CTXT_HW_BUSY_BIT_MASK 0x1
#define CMDQ_CTXT_CURR_WQE_PAGE_PFN_MASK 0xFFFFFFFFFFFFF
#define CMDQ_CTXT_EQ_ID_MASK 0x1F
#define CMDQ_CTXT_CEQ_ARM_MASK 0x1
#define CMDQ_CTXT_CEQ_EN_MASK 0x1
#define CMDQ_CTXT_HW_BUSY_BIT_MASK 0x1
#define CMDQ_CTXT_PAGE_INFO_SET(val, member) \
(((u64)(val) & CMDQ_CTXT_##member##_MASK) \
<< CMDQ_CTXT_##member##_SHIFT)
<< CMDQ_CTXT_##member##_SHIFT)
#define CMDQ_CTXT_PAGE_INFO_GET(val, member) \
(((u64)(val) >> CMDQ_CTXT_##member##_SHIFT) \
& CMDQ_CTXT_##member##_MASK)
#define CMDQ_CTXT_WQ_BLOCK_PFN_SHIFT 0
#define CMDQ_CTXT_CI_SHIFT 52
#define CMDQ_CTXT_WQ_BLOCK_PFN_SHIFT 0
#define CMDQ_CTXT_CI_SHIFT 52
#define CMDQ_CTXT_WQ_BLOCK_PFN_MASK 0xFFFFFFFFFFFFF
#define CMDQ_CTXT_CI_MASK 0xFFF
#define CMDQ_CTXT_WQ_BLOCK_PFN_MASK 0xFFFFFFFFFFFFF
#define CMDQ_CTXT_CI_MASK 0xFFF
#define CMDQ_CTXT_BLOCK_INFO_SET(val, member) \
(((u64)(val) & CMDQ_CTXT_##member##_MASK) \
<< CMDQ_CTXT_##member##_SHIFT)
<< CMDQ_CTXT_##member##_SHIFT)
#define CMDQ_CTXT_BLOCK_INFO_GET(val, member) \
(((u64)(val) >> CMDQ_CTXT_##member##_SHIFT) \
& CMDQ_CTXT_##member##_MASK)
#define SAVED_DATA_ARM_SHIFT 31
#define SAVED_DATA_ARM_SHIFT 31
#define SAVED_DATA_ARM_MASK 0x1U
#define SAVED_DATA_ARM_MASK 0x1U
#define SAVED_DATA_SET(val, member) \
(((val) & SAVED_DATA_##member##_MASK) \
<< SAVED_DATA_##member##_SHIFT)
<< SAVED_DATA_##member##_SHIFT)
#define SAVED_DATA_CLEAR(val, member) \
((val) & (~(SAVED_DATA_##member##_MASK \
<< SAVED_DATA_##member##_SHIFT)))
<< SAVED_DATA_##member##_SHIFT)))
#define WQE_ERRCODE_VAL_SHIFT 20
#define WQE_ERRCODE_VAL_SHIFT 20
#define WQE_ERRCODE_VAL_MASK 0xF
#define WQE_ERRCODE_VAL_MASK 0xF
#define WQE_ERRCODE_GET(val, member) \
(((val) >> WQE_ERRCODE_##member##_SHIFT) & \
WQE_ERRCODE_##member##_MASK)
WQE_ERRCODE_##member##_MASK)
#define CEQE_CMDQ_TYPE_SHIFT 0
#define CEQE_CMDQ_TYPE_SHIFT 0
#define CEQE_CMDQ_TYPE_MASK 0x7
#define CEQE_CMDQ_TYPE_MASK 0x7
#define CEQE_CMDQ_GET(val, member) \
(((val) >> CEQE_CMDQ_##member##_SHIFT) & CEQE_CMDQ_##member##_MASK)
......@@ -169,28 +169,28 @@
#define CMDQ_DB_PI_OFF(pi) (((u16)LOWER_8_BITS(pi)) << 3)
#define CMDQ_DB_ADDR(db_base, pi) \
(((u8 *)db_base + HINIC_DB_OFF) + CMDQ_DB_PI_OFF(pi))
(((u8 *)(db_base) + HINIC_DB_OFF) + CMDQ_DB_PI_OFF(pi))
#define CMDQ_PFN_SHIFT 12
#define CMDQ_PFN(addr) ((addr) >> CMDQ_PFN_SHIFT)
#define FIRST_DATA_TO_WRITE_LAST sizeof(u64)
#define WQE_LCMD_SIZE 64
#define WQE_SCMD_SIZE 64
#define WQE_LCMD_SIZE 64
#define WQE_SCMD_SIZE 64
#define COMPLETE_LEN 3
#define COMPLETE_LEN 3
#define CMDQ_WQEBB_SIZE 64
#define CMDQ_WQE_SIZE 64
#define CMDQ_WQEBB_SIZE 64
#define CMDQ_WQE_SIZE 64
#define CMDQ_WQ_PAGE_SIZE 4096
#define CMDQ_WQ_PAGE_SIZE 4096
#define WQE_NUM_WQEBBS(wqe_size, wq) \
((u16)(ALIGN((u32)(wqe_size), (wq)->wqebb_size) / (wq)->wqebb_size))
#define cmdq_to_cmdqs(cmdq) container_of((cmdq) - (cmdq)->cmdq_type, \
struct hinic_cmdqs, cmdq[0])
struct hinic_cmdqs, cmdq[0])
#define CMDQ_SEND_CMPT_CODE 10
#define CMDQ_COMPLETE_CMPT_CODE 11
......@@ -385,10 +385,10 @@ static void cmdq_wqe_fill(void *dst, const void *src)
static void cmdq_prepare_wqe_ctrl(struct hinic_cmdq_wqe *wqe, int wrapped,
enum hinic_ack_type ack_type,
enum hinic_mod_type mod, u8 cmd, u16 prod_idx,
enum completion_format complete_format,
enum data_format data_format,
enum bufdesc_len buf_len)
enum hinic_mod_type mod, u8 cmd, u16 prod_idx,
enum completion_format complete_format,
enum data_format data_format,
enum bufdesc_len buf_len)
{
struct hinic_ctrl *ctrl;
enum ctrl_sect_len ctrl_len;
......@@ -436,10 +436,10 @@ static void cmdq_prepare_wqe_ctrl(struct hinic_cmdq_wqe *wqe, int wrapped,
static void cmdq_set_lcmd_wqe(struct hinic_cmdq_wqe *wqe,
enum cmdq_cmd_type cmd_type,
struct hinic_cmd_buf *buf_in,
struct hinic_cmd_buf *buf_out, int wrapped,
enum hinic_ack_type ack_type,
enum hinic_mod_type mod, u8 cmd, u16 prod_idx)
struct hinic_cmd_buf *buf_in,
struct hinic_cmd_buf *buf_out, int wrapped,
enum hinic_ack_type ack_type,
enum hinic_mod_type mod, u8 cmd, u16 prod_idx)
{
struct hinic_cmdq_wqe_lcmd *wqe_lcmd = &wqe->wqe_lcmd;
enum completion_format complete_format = COMPLETE_DIRECT;
......@@ -465,7 +465,7 @@ static void cmdq_set_lcmd_wqe(struct hinic_cmdq_wqe *wqe,
cmdq_prepare_wqe_ctrl(wqe, wrapped, ack_type, mod, cmd,
prod_idx, complete_format, DATA_SGE,
BUFDESC_LCMD_LEN);
BUFDESC_LCMD_LEN);
cmdq_set_lcmd_bufdesc(wqe_lcmd, buf_in);
}
......@@ -706,10 +706,10 @@ static int cmdq_sync_cmd_direct_resp(struct hinic_cmdq *cmdq,
static int cmdq_sync_cmd_detail_resp(struct hinic_cmdq *cmdq,
enum hinic_ack_type ack_type,
enum hinic_mod_type mod, u8 cmd,
struct hinic_cmd_buf *buf_in,
struct hinic_cmd_buf *buf_out,
u32 timeout)
enum hinic_mod_type mod, u8 cmd,
struct hinic_cmd_buf *buf_in,
struct hinic_cmd_buf *buf_out,
u32 timeout)
{
struct hinic_wq *wq = cmdq->wq;
struct hinic_cmdq_wqe *curr_wqe, wqe;
......@@ -913,7 +913,7 @@ static int cmdq_set_arm_bit(struct hinic_cmdq *cmdq, void *buf_in, u16 in_size)
cmdq_set_inline_wqe(&wqe, SYNC_CMD_DIRECT_RESP, buf_in, in_size, NULL,
wrapped, HINIC_ACK_TYPE_CMDQ, HINIC_MOD_COMM,
CMDQ_SET_ARM_CMD, curr_prod_idx);
CMDQ_SET_ARM_CMD, curr_prod_idx);
/* The data that is written to HW should be in Big Endian Format */
hinic_cpu_to_be32(&wqe, wqe_size);
......@@ -1038,7 +1038,7 @@ EXPORT_SYMBOL(hinic_cmdq_detail_resp);
int hinic_cmdq_async(void *hwdev, enum hinic_ack_type ack_type,
enum hinic_mod_type mod, u8 cmd,
struct hinic_cmd_buf *buf_in)
struct hinic_cmd_buf *buf_in)
{
struct hinic_cmdqs *cmdqs;
int err = cmdq_params_valid(hwdev, buf_in);
......@@ -1494,7 +1494,7 @@ int hinic_cmdqs_init(struct hinic_hwdev *hwdev)
cmdqs->cmd_buf_pool = dma_pool_create("hinic_cmdq", hwdev->dev_hdl,
HINIC_CMDQ_BUF_SIZE,
HINIC_CMDQ_BUF_SIZE, 0ULL);
HINIC_CMDQ_BUF_SIZE, 0ULL);
if (!cmdqs->cmd_buf_pool) {
sdk_err(hwdev->dev_hdl, "Failed to create cmdq buffer pool\n");
err = -ENOMEM;
......
drivers/net/ethernet/huawei/hinic/hinic_csr.h
浏览文件 @ e6a07712
......@@ -92,12 +92,12 @@
(pg_num) * HINIC_CSR_EQ_PAGE_OFF_STRIDE + 4)
#define HINIC_EQ_HI_PHYS_ADDR_REG(type, q_id, pg_num) \
((u32)((type == HINIC_AEQ) ? \
((u32)(((type) == HINIC_AEQ) ? \
HINIC_AEQ_HI_PHYS_ADDR_REG(q_id, pg_num) : \
HINIC_CEQ_HI_PHYS_ADDR_REG(q_id, pg_num)))
#define HINIC_EQ_LO_PHYS_ADDR_REG(type, q_id, pg_num) \
((u32)((type == HINIC_AEQ) ? \
((u32)(((type) == HINIC_AEQ) ? \
HINIC_AEQ_LO_PHYS_ADDR_REG(q_id, pg_num) : \
HINIC_CEQ_LO_PHYS_ADDR_REG(q_id, pg_num)))
......
drivers/net/ethernet/huawei/hinic/hinic_ctx_def.h
浏览文件 @ e6a07712
......@@ -20,16 +20,16 @@
#define HINIC_CEQE_QN_MASK 0x3FFU
#define HINIC_Q_CTXT_MAX 42
#define HINIC_Q_CTXT_MAX 42
#define HINIC_RQ_CQ_MAX 128
#define HINIC_RQ_CQ_MAX 128
#define MAX_WQE_SIZE(max_sge, wqebb_size) \
(((max_sge) <= 2) ? (wqebb_size) : \
((ALIGN(((max_sge) - 2), 4) / 4 + 1) * (wqebb_size)))
/* performance: ci addr RTE_CACHE_SIZE(64B) alignment */
#define HINIC_CI_Q_ADDR_SIZE (64)
#define HINIC_CI_Q_ADDR_SIZE 64
#define CI_TABLE_SIZE(num_qps, pg_sz) \
(ALIGN((num_qps) * HINIC_CI_Q_ADDR_SIZE, pg_sz))
......@@ -40,8 +40,8 @@
#define HINIC_CI_PADDR(base_paddr, q_id) ((base_paddr) + \
(q_id) * HINIC_CI_Q_ADDR_SIZE)
#define Q_CTXT_SIZE 48
#define TSO_LRO_CTXT_SIZE 240
#define Q_CTXT_SIZE 48
#define TSO_LRO_CTXT_SIZE 240
#define SQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
(((max_rqs) + (max_sqs)) * TSO_LRO_CTXT_SIZE \
......@@ -57,128 +57,128 @@
#define RQ_CTXT_SIZE(num_rqs) ((u16)(sizeof(struct hinic_qp_ctxt_header) \
+ (num_rqs) * sizeof(struct hinic_rq_ctxt)))
#define SQ_CTXT_CEQ_ATTR_CEQ_ID_SHIFT 8
#define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT 13
#define SQ_CTXT_CEQ_ATTR_EN_SHIFT 23
#define SQ_CTXT_CEQ_ATTR_ARM_SHIFT 31
#define SQ_CTXT_CEQ_ATTR_CEQ_ID_SHIFT 8
#define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT 13
#define SQ_CTXT_CEQ_ATTR_EN_SHIFT 23
#define SQ_CTXT_CEQ_ATTR_ARM_SHIFT 31
#define SQ_CTXT_CEQ_ATTR_CEQ_ID_MASK 0x1FU
#define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FFU
#define SQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
#define SQ_CTXT_CEQ_ATTR_ARM_MASK 0x1U
#define SQ_CTXT_CEQ_ATTR_CEQ_ID_MASK 0x1FU
#define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FFU
#define SQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
#define SQ_CTXT_CEQ_ATTR_ARM_MASK 0x1U
#define SQ_CTXT_CEQ_ATTR_SET(val, member) (((val) & \
SQ_CTXT_CEQ_ATTR_##member##_MASK) \
<< SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
#define SQ_CTXT_CEQ_ATTR_SET(val, member) \
(((val) & SQ_CTXT_CEQ_ATTR_##member##_MASK) \
<< SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
#define SQ_CTXT_CI_IDX_SHIFT 11
#define SQ_CTXT_CI_OWNER_SHIFT 23
#define SQ_CTXT_CI_IDX_SHIFT 11
#define SQ_CTXT_CI_OWNER_SHIFT 23
#define SQ_CTXT_CI_IDX_MASK 0xFFFU
#define SQ_CTXT_CI_OWNER_MASK 0x1U
#define SQ_CTXT_CI_IDX_MASK 0xFFFU
#define SQ_CTXT_CI_OWNER_MASK 0x1U
#define SQ_CTXT_CI_SET(val, member) (((val) & \
SQ_CTXT_CI_##member##_MASK) \
<< SQ_CTXT_CI_##member##_SHIFT)
#define SQ_CTXT_CI_SET(val, member) \
(((val) & SQ_CTXT_CI_##member##_MASK) \
<< SQ_CTXT_CI_##member##_SHIFT)
#define SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
#define SQ_CTXT_WQ_PAGE_PI_SHIFT 20
#define SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
#define SQ_CTXT_WQ_PAGE_PI_SHIFT 20
#define SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
#define SQ_CTXT_WQ_PAGE_PI_MASK 0xFFFU
#define SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
#define SQ_CTXT_WQ_PAGE_PI_MASK 0xFFFU
#define SQ_CTXT_WQ_PAGE_SET(val, member) (((val) & \
SQ_CTXT_WQ_PAGE_##member##_MASK) \
<< SQ_CTXT_WQ_PAGE_##member##_SHIFT)
#define SQ_CTXT_WQ_PAGE_SET(val, member) \
(((val) & SQ_CTXT_WQ_PAGE_##member##_MASK) \
<< SQ_CTXT_WQ_PAGE_##member##_SHIFT)
#define SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
#define SQ_CTXT_PREF_CACHE_MAX_SHIFT 14
#define SQ_CTXT_PREF_CACHE_MIN_SHIFT 25
#define SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
#define SQ_CTXT_PREF_CACHE_MAX_SHIFT 14
#define SQ_CTXT_PREF_CACHE_MIN_SHIFT 25
#define SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFFU
#define SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FFU
#define SQ_CTXT_PREF_CACHE_MIN_MASK 0x7FU
#define SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFFU
#define SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FFU
#define SQ_CTXT_PREF_CACHE_MIN_MASK 0x7FU
#define SQ_CTXT_PREF_WQ_PFN_HI_SHIFT 0
#define SQ_CTXT_PREF_CI_SHIFT 20
#define SQ_CTXT_PREF_WQ_PFN_HI_SHIFT 0
#define SQ_CTXT_PREF_CI_SHIFT 20
#define SQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
#define SQ_CTXT_PREF_CI_MASK 0xFFFU
#define SQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
#define SQ_CTXT_PREF_CI_MASK 0xFFFU
#define SQ_CTXT_PREF_SET(val, member) (((val) & \
SQ_CTXT_PREF_##member##_MASK) \
<< SQ_CTXT_PREF_##member##_SHIFT)
#define SQ_CTXT_PREF_SET(val, member) \
(((val) & SQ_CTXT_PREF_##member##_MASK) \
<< SQ_CTXT_PREF_##member##_SHIFT)
#define SQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
#define SQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
#define SQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
#define SQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
#define SQ_CTXT_WQ_BLOCK_SET(val, member) (((val) & \
SQ_CTXT_WQ_BLOCK_##member##_MASK) \
<< SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
#define SQ_CTXT_WQ_BLOCK_SET(val, member) \
(((val) & SQ_CTXT_WQ_BLOCK_##member##_MASK) \
<< SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
#define RQ_CTXT_CEQ_ATTR_EN_SHIFT 0
#define RQ_CTXT_CEQ_ATTR_OWNER_SHIFT 1
#define RQ_CTXT_CEQ_ATTR_EN_SHIFT 0
#define RQ_CTXT_CEQ_ATTR_OWNER_SHIFT 1
#define RQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
#define RQ_CTXT_CEQ_ATTR_OWNER_MASK 0x1U
#define RQ_CTXT_CEQ_ATTR_EN_MASK 0x1U
#define RQ_CTXT_CEQ_ATTR_OWNER_MASK 0x1U
#define RQ_CTXT_CEQ_ATTR_SET(val, member) (((val) & \
RQ_CTXT_CEQ_ATTR_##member##_MASK) \
<< RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
#define RQ_CTXT_CEQ_ATTR_SET(val, member) \
(((val) & RQ_CTXT_CEQ_ATTR_##member##_MASK) \
<< RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
#define RQ_CTXT_PI_IDX_SHIFT 0
#define RQ_CTXT_PI_INTR_SHIFT 22
#define RQ_CTXT_PI_CEQ_ARM_SHIFT 31
#define RQ_CTXT_PI_IDX_SHIFT 0
#define RQ_CTXT_PI_INTR_SHIFT 22
#define RQ_CTXT_PI_CEQ_ARM_SHIFT 31
#define RQ_CTXT_PI_IDX_MASK 0xFFFU
#define RQ_CTXT_PI_INTR_MASK 0x3FFU
#define RQ_CTXT_PI_CEQ_ARM_MASK 0x1U
#define RQ_CTXT_PI_IDX_MASK 0xFFFU
#define RQ_CTXT_PI_INTR_MASK 0x3FFU
#define RQ_CTXT_PI_CEQ_ARM_MASK 0x1U
#define RQ_CTXT_PI_SET(val, member) (((val) & \
RQ_CTXT_PI_##member##_MASK) << \
RQ_CTXT_PI_##member##_SHIFT)
#define RQ_CTXT_PI_SET(val, member) \
(((val) & RQ_CTXT_PI_##member##_MASK) << \
RQ_CTXT_PI_##member##_SHIFT)
#define RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
#define RQ_CTXT_WQ_PAGE_CI_SHIFT 20
#define RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
#define RQ_CTXT_WQ_PAGE_CI_SHIFT 20
#define RQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
#define RQ_CTXT_WQ_PAGE_CI_MASK 0xFFFU
#define RQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFFU
#define RQ_CTXT_WQ_PAGE_CI_MASK 0xFFFU
#define RQ_CTXT_WQ_PAGE_SET(val, member) (((val) & \
RQ_CTXT_WQ_PAGE_##member##_MASK) << \
RQ_CTXT_WQ_PAGE_##member##_SHIFT)
#define RQ_CTXT_WQ_PAGE_SET(val, member) \
(((val) & RQ_CTXT_WQ_PAGE_##member##_MASK) << \
RQ_CTXT_WQ_PAGE_##member##_SHIFT)
#define RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
#define RQ_CTXT_PREF_CACHE_MAX_SHIFT 14
#define RQ_CTXT_PREF_CACHE_MIN_SHIFT 25
#define RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
#define RQ_CTXT_PREF_CACHE_MAX_SHIFT 14
#define RQ_CTXT_PREF_CACHE_MIN_SHIFT 25
#define RQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFFU
#define RQ_CTXT_PREF_CACHE_MAX_MASK 0x7FFU
#define RQ_CTXT_PREF_CACHE_MIN_MASK 0x7FU
#define RQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFFU
#define RQ_CTXT_PREF_CACHE_MAX_MASK 0x7FFU
#define RQ_CTXT_PREF_CACHE_MIN_MASK 0x7FU
#define RQ_CTXT_PREF_WQ_PFN_HI_SHIFT 0
#define RQ_CTXT_PREF_CI_SHIFT 20
#define RQ_CTXT_PREF_WQ_PFN_HI_SHIFT 0
#define RQ_CTXT_PREF_CI_SHIFT 20
#define RQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
#define RQ_CTXT_PREF_CI_MASK 0xFFFU
#define RQ_CTXT_PREF_WQ_PFN_HI_MASK 0xFFFFFU
#define RQ_CTXT_PREF_CI_MASK 0xFFFU
#define RQ_CTXT_PREF_SET(val, member) (((val) & \
RQ_CTXT_PREF_##member##_MASK) << \
RQ_CTXT_PREF_##member##_SHIFT)
#define RQ_CTXT_PREF_SET(val, member) \
(((val) & RQ_CTXT_PREF_##member##_MASK) << \
RQ_CTXT_PREF_##member##_SHIFT)
#define RQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
#define RQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT 0
#define RQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
#define RQ_CTXT_WQ_BLOCK_PFN_HI_MASK 0x7FFFFFU
#define RQ_CTXT_WQ_BLOCK_SET(val, member) (((val) & \
RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
#define RQ_CTXT_WQ_BLOCK_SET(val, member) \
(((val) & RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
#define SIZE_16BYTES(size) (ALIGN((size), 16) >> 4)
#define SIZE_16BYTES(size) (ALIGN((size), 16) >> 4)
#define WQ_PAGE_PFN_SHIFT 12
#define WQ_BLOCK_PFN_SHIFT 9
#define WQ_PAGE_PFN_SHIFT 12
#define WQ_BLOCK_PFN_SHIFT 9
#define WQ_PAGE_PFN(page_addr) ((page_addr) >> WQ_PAGE_PFN_SHIFT)
#define WQ_BLOCK_PFN(page_addr) ((page_addr) >> WQ_BLOCK_PFN_SHIFT)
......
drivers/net/ethernet/huawei/hinic/hinic_dbgtool_knl.c
浏览文件 @ e6a07712
......@@ -46,7 +46,7 @@ struct ffm_intr_info {
u32 err_csr_value;
};
#define DBGTOOL_MSG_MAX_SIZE 2048ULL
#define DBGTOOL_MSG_MAX_SIZE 2048ULL
#define HINIC_SELF_CMD_UP2PF_FFM 0x26
void *g_card_node_array[MAX_CARD_NUM] = {0};
......@@ -57,9 +57,9 @@ struct mutex g_addr_lock;
int card_id;
/* dbgtool character device name, class name, dev path */
#define CHR_DEV_DBGTOOL "dbgtool_chr_dev"
#define CLASS_DBGTOOL "dbgtool_class"
#define DBGTOOL_DEV_PATH "/dev/dbgtool_chr_dev"
#define CHR_DEV_DBGTOOL "dbgtool_chr_dev"
#define CLASS_DBGTOOL "dbgtool_class"
#define DBGTOOL_DEV_PATH "/dev/dbgtool_chr_dev"
struct dbgtool_k_glb_info {
struct semaphore dbgtool_sem;
......
drivers/net/ethernet/huawei/hinic/hinic_dcb.c
浏览文件 @ e6a07712
......@@ -120,8 +120,6 @@ void hinic_init_ieee_settings(struct hinic_nic_dev *nic_dev)
if (dcb_cfg->tc_cfg[i].pfc_en)
pfc->pfc_en |= (u8)BIT(i);
}
return;
}
static int hinic_set_up_cos_map(struct hinic_nic_dev *nic_dev,
......@@ -1273,7 +1271,7 @@ u8 hinic_dcbnl_set_all(struct net_device *netdev)
}
static int hinic_dcbnl_ieee_get_ets(struct net_device *netdev,
struct ieee_ets *ets)
struct ieee_ets *ets)
{
struct hinic_nic_dev *nic_dev = netdev_priv(netdev);
struct ieee_ets *my_ets = &nic_dev->hinic_ieee_ets;
......@@ -1288,7 +1286,7 @@ static int hinic_dcbnl_ieee_get_ets(struct net_device *netdev,
}
static int hinic_dcbnl_ieee_set_ets(struct net_device *netdev,
struct ieee_ets *ets)
struct ieee_ets *ets)
{
struct hinic_nic_dev *nic_dev = netdev_priv(netdev);
struct hinic_dcb_config *dcb_cfg = &nic_dev->dcb_cfg;
......@@ -1354,7 +1352,7 @@ static int hinic_dcbnl_ieee_set_ets(struct net_device *netdev,
}
static int hinic_dcbnl_ieee_get_pfc(struct net_device *netdev,
struct ieee_pfc *pfc)
struct ieee_pfc *pfc)
{
struct hinic_nic_dev *nic_dev = netdev_priv(netdev);
struct ieee_pfc *my_pfc = &nic_dev->hinic_ieee_pfc;
......@@ -1366,7 +1364,7 @@ static int hinic_dcbnl_ieee_get_pfc(struct net_device *netdev,
}
static int hinic_dcbnl_ieee_set_pfc(struct net_device *netdev,
struct ieee_pfc *pfc)
struct ieee_pfc *pfc)
{
struct hinic_nic_dev *nic_dev = netdev_priv(netdev);
struct hinic_dcb_config *dcb_cfg = &nic_dev->dcb_cfg;
......
drivers/net/ethernet/huawei/hinic/hinic_dfx_def.h
浏览文件 @ e6a07712
......@@ -139,9 +139,9 @@ struct hinic_show_item {
u64 value;
};
#define UP_UPDATEFW_TIME_OUT_VAL 20000U
#define UP_UPDATEFW_TIME_OUT_VAL 20000U
#define UCODE_COMP_TIME_OUT_VAL 0xFF00000
#define NIC_TOOL_MAGIC 'x'
#define NIC_TOOL_MAGIC 'x'
enum hinic_nictool_drv_cap {
NICTOOL_SUPPORT_API_CSR = 0x1,
......
drivers/net/ethernet/huawei/hinic/hinic_eqs.c
浏览文件 @ e6a07712
......@@ -51,15 +51,15 @@
#define AEQ_CTRL_0_GET(val, member) \
(((val) >> AEQ_CTRL_0_##member##_SHIFT) & \
AEQ_CTRL_0_##member##_MASK)
AEQ_CTRL_0_##member##_MASK)
#define AEQ_CTRL_0_SET(val, member) \
(((val) & AEQ_CTRL_0_##member##_MASK) << \
AEQ_CTRL_0_##member##_SHIFT)
AEQ_CTRL_0_##member##_SHIFT)
#define AEQ_CTRL_0_CLEAR(val, member) \
((val) & (~(AEQ_CTRL_0_##member##_MASK \
<< AEQ_CTRL_0_##member##_SHIFT)))
<< AEQ_CTRL_0_##member##_SHIFT)))
#define AEQ_CTRL_1_LEN_SHIFT 0
#define AEQ_CTRL_1_FUNC_OWN_SHIFT 21
......@@ -73,15 +73,15 @@
#define AEQ_CTRL_1_GET(val, member) \
(((val) >> AEQ_CTRL_1_##member##_SHIFT) & \
AEQ_CTRL_1_##member##_MASK)
AEQ_CTRL_1_##member##_MASK)
#define AEQ_CTRL_1_SET(val, member) \
(((val) & AEQ_CTRL_1_##member##_MASK) << \
AEQ_CTRL_1_##member##_SHIFT)
AEQ_CTRL_1_##member##_SHIFT)
#define AEQ_CTRL_1_CLEAR(val, member) \
((val) & (~(AEQ_CTRL_1_##member##_MASK \
<< AEQ_CTRL_1_##member##_SHIFT)))
<< AEQ_CTRL_1_##member##_SHIFT)))
#define HINIC_EQ_PROD_IDX_MASK 0xFFFFF
#define HINIC_TASK_PROCESS_EQE_LIMIT 1024
......@@ -118,7 +118,7 @@ MODULE_PARM_DESC(g_num_ceqe_in_tasklet,
#define CEQ_CTRL_0_SET(val, member) \
(((val) & CEQ_CTRL_0_##member##_MASK) << \
CEQ_CTRL_0_##member##_SHIFT)
CEQ_CTRL_0_##member##_SHIFT)
#define CEQ_CTRL_1_LEN_SHIFT 0
#define CEQ_CTRL_1_PAGE_SIZE_SHIFT 28
......@@ -128,7 +128,7 @@ MODULE_PARM_DESC(g_num_ceqe_in_tasklet,
#define CEQ_CTRL_1_SET(val, member) \
(((val) & CEQ_CTRL_1_##member##_MASK) << \
CEQ_CTRL_1_##member##_SHIFT)
CEQ_CTRL_1_##member##_SHIFT)
#define EQ_ELEM_DESC_TYPE_SHIFT 0
#define EQ_ELEM_DESC_SRC_SHIFT 7
......@@ -142,7 +142,7 @@ MODULE_PARM_DESC(g_num_ceqe_in_tasklet,
#define EQ_ELEM_DESC_GET(val, member) \
(((val) >> EQ_ELEM_DESC_##member##_SHIFT) & \
EQ_ELEM_DESC_##member##_MASK)
EQ_ELEM_DESC_##member##_MASK)
#define EQ_CONS_IDX_CONS_IDX_SHIFT 0
#define EQ_CONS_IDX_XOR_CHKSUM_SHIFT 24
......@@ -154,11 +154,11 @@ MODULE_PARM_DESC(g_num_ceqe_in_tasklet,
#define EQ_CONS_IDX_SET(val, member) \
(((val) & EQ_CONS_IDX_##member##_MASK) << \
EQ_CONS_IDX_##member##_SHIFT)
EQ_CONS_IDX_##member##_SHIFT)
#define EQ_CONS_IDX_CLEAR(val, member) \
((val) & (~(EQ_CONS_IDX_##member##_MASK \
<< EQ_CONS_IDX_##member##_SHIFT)))
<< EQ_CONS_IDX_##member##_SHIFT)))
#define EQ_WRAPPED(eq) ((u32)(eq)->wrapped << EQ_VALID_SHIFT)
......@@ -546,7 +546,7 @@ static bool aeq_irq_handler(struct hinic_eq *eq)
&aeqs->aeq_sw_cb_state[sw_event]);
if (aeqs->aeq_swe_cb[sw_event] &&
test_bit(HINIC_AEQ_SW_CB_REG,
&aeqs->aeq_sw_cb_state[sw_event])) {
&aeqs->aeq_sw_cb_state[sw_event])) {
lev = aeqs->aeq_swe_cb[sw_event](aeqs->hwdev,
ucode_event,
aeqe_data);
......@@ -560,7 +560,7 @@ static bool aeq_irq_handler(struct hinic_eq *eq)
&aeqs->aeq_hw_cb_state[event]);
if (aeqs->aeq_hwe_cb[event] &&
test_bit(HINIC_AEQ_HW_CB_REG,
&aeqs->aeq_hw_cb_state[event]))
&aeqs->aeq_hw_cb_state[event]))
aeqs->aeq_hwe_cb[event](aeqs->hwdev,
aeqe_pos->aeqe_data, size);
clear_bit(HINIC_AEQ_HW_CB_RUNNING,
......@@ -1064,6 +1064,7 @@ static void free_eq_pages(struct hinic_eq *eq)
kfree(eq->virt_addr);
kfree(eq->dma_addr);
}
static inline u32 get_page_size(struct hinic_eq *eq)
{
u32 total_size;
......@@ -1087,6 +1088,7 @@ static inline u32 get_page_size(struct hinic_eq *eq)
return EQ_MIN_PAGE_SIZE << n;
}
/**
* init_eq - initialize eq
* @eq: the event queue
......
drivers/net/ethernet/huawei/hinic/hinic_eqs.h
浏览文件 @ e6a07712
......@@ -71,6 +71,7 @@ struct hinic_eq_work {
struct hinic_ceq_tasklet_data {
void *data;
};
struct hinic_eq {
struct hinic_hwdev *hwdev;
u16 q_id;
......@@ -86,7 +87,7 @@ struct hinic_eq {
u16 num_pages;
u32 num_elem_in_pg;
struct irq_info eq_irq;
struct irq_info eq_irq;
char irq_name[EQ_IRQ_NAME_LEN];
dma_addr_t *dma_addr;
......
drivers/net/ethernet/huawei/hinic/hinic_ethtool.c
浏览文件 @ e6a07712
......@@ -337,12 +337,12 @@ void hinic_get_io_stats(struct hinic_nic_dev *nic_dev,
}
}
#define LP_DEFAULT_TIME (5) /* seconds */
#define LP_PKT_LEN (1514)
#define OBJ_STR_MAX_LEN (32)
#define SET_LINK_STR_MAX_LEN (128)
#define LP_DEFAULT_TIME 5 /* seconds */
#define LP_PKT_LEN 1514
#define OBJ_STR_MAX_LEN 32
#define SET_LINK_STR_MAX_LEN 128
#define PORT_DOWN_ERR_IDX 0
#define PORT_DOWN_ERR_IDX 0
enum diag_test_index {
INTERNAL_LP_TEST = 0,
EXTERNAL_LP_TEST = 1,
......@@ -684,23 +684,23 @@ static int hinic_get_settings(struct net_device *netdev,
}
static int hinic_get_link_ksettings(struct net_device *netdev,
struct ethtool_link_ksettings *link_settings)
struct ethtool_link_ksettings *cmd)
{
struct cmd_link_settings settings = {0};
struct ethtool_link_settings *base = &link_settings->base;
struct ethtool_link_settings *base = &cmd->base;
int err;
ethtool_link_ksettings_zero_link_mode(link_settings, supported);
ethtool_link_ksettings_zero_link_mode(link_settings, advertising);
ethtool_link_ksettings_zero_link_mode(cmd, supported);
ethtool_link_ksettings_zero_link_mode(cmd, advertising);
err = get_link_settings(netdev, &settings);
if (err)
return err;
bitmap_copy(link_settings->link_modes.supported,
bitmap_copy(cmd->link_modes.supported,
(unsigned long *)&settings.supported,
__ETHTOOL_LINK_MODE_MASK_NBITS);
bitmap_copy(link_settings->link_modes.advertising,
bitmap_copy(cmd->link_modes.advertising,
(unsigned long *)&settings.advertising,
__ETHTOOL_LINK_MODE_MASK_NBITS);
......@@ -868,11 +868,11 @@ static int hinic_set_settings(struct net_device *netdev,
}
static int hinic_set_link_ksettings(struct net_device *netdev,
const struct ethtool_link_ksettings *link_settings)
const struct ethtool_link_ksettings *cmd)
{
/* Only support to set autoneg and speed */
return set_link_settings(netdev, link_settings->base.autoneg,
link_settings->base.speed);
return set_link_settings(netdev, cmd->base.autoneg,
cmd->base.speed);
}
static void hinic_get_drvinfo(struct net_device *netdev,
......@@ -1387,27 +1387,27 @@ static int is_coalesce_legal(struct net_device *netdev,
#define CHECK_COALESCE_ALIGN(coal, item, unit) \
do { \
if (coal->item % (unit)) \
if ((coal)->item % (unit)) \
nicif_warn(nic_dev, drv, netdev, \
"%s in %d units, change to %d\n", \
#item, (unit), ALIGN_DOWN(coal->item, unit));\
#item, (unit), ALIGN_DOWN((coal)->item, unit));\
} while (0)
#define CHECK_COALESCE_CHANGED(coal, item, unit, ori_val, obj_str) \
do { \
if ((coal->item / (unit)) != (ori_val)) \
if (((coal)->item / (unit)) != (ori_val)) \
nicif_info(nic_dev, drv, netdev, \
"Change %s from %d to %d %s\n", \
#item, (ori_val) * (unit), \
ALIGN_DOWN(coal->item, unit), (obj_str)); \
ALIGN_DOWN((coal)->item, unit), (obj_str));\
} while (0)
#define CHECK_PKT_RATE_CHANGED(coal, item, ori_val, obj_str) \
do { \
if (coal->item != (ori_val)) \
if ((coal)->item != (ori_val)) \
nicif_info(nic_dev, drv, netdev, \
"Change %s from %llu to %u %s\n", \
#item, (ori_val), coal->item, (obj_str)); \
#item, (ori_val), (coal)->item, (obj_str));\
} while (0)
static int __hinic_set_coalesce(struct net_device *netdev,
......
drivers/net/ethernet/huawei/hinic/hinic_hw.h
浏览文件 @ e6a07712
......@@ -70,8 +70,8 @@ int hinic_msg_to_mgmt_async(void *hwdev, enum hinic_mod_type mod, u8 cmd,
void *buf_in, u16 in_size);
int hinic_mbox_to_vf(void *hwdev, enum hinic_mod_type mod,
u16 vf_id, u8 cmd, void *buf_in, u16 in_size,
void *buf_out, u16 *out_size, u32 timeout);
u16 vf_id, u8 cmd, void *buf_in, u16 in_size,
void *buf_out, u16 *out_size, u32 timeout);
int hinic_api_cmd_write_nack(void *hwdev, u8 dest,
void *cmd, u16 size);
......@@ -155,7 +155,8 @@ int hinic_aeq_register_swe_cb(void *hwdev, enum hinic_aeq_sw_type event,
void hinic_aeq_unregister_swe_cb(void *hwdev, enum hinic_aeq_sw_type event);
typedef void (*hinic_mgmt_msg_cb)(void *hwdev, void *pri_handle,
u8 cmd, void *buf_in, u16 in_size, void *buf_out, u16 *out_size);
u8 cmd, void *buf_in, u16 in_size,
void *buf_out, u16 *out_size);
int hinic_register_mgmt_msg_cb(void *hwdev,
enum hinic_mod_type mod, void *pri_handle,
......@@ -428,6 +429,7 @@ enum hinic_service_mode {
HINIC_WORK_MODE_NIC,
HINIC_WORK_MODE_INVALID = 0xFF,
};
enum hinic_service_mode hinic_get_service_mode(void *hwdev);
int hinic_slq_init(void *dev, int num_wqs);
......@@ -439,7 +441,8 @@ u64 hinic_slq_get_addr(void *handle, u16 index);
u64 hinic_slq_get_first_pageaddr(void *handle);
typedef void (*comm_up_self_msg_proc)(void *handle, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size);
u16 in_size, void *buf_out,
u16 *out_size);
void hinic_comm_recv_mgmt_self_cmd_reg(void *hwdev, u8 cmd,
comm_up_self_msg_proc proc);
......@@ -668,7 +671,7 @@ enum hinic_ucode_event_type {
};
typedef void (*hinic_event_handler)(void *handle,
struct hinic_event_info *event);
struct hinic_event_info *event);
/* only register once */
void hinic_event_register(void *dev, void *pri_handle,
......@@ -751,11 +754,11 @@ struct hinic_hw_pf_infos {
int hinic_get_hw_pf_infos(void *hwdev, struct hinic_hw_pf_infos *infos);
int hinic_set_ip_check(void *hwdev, bool ip_check_ctl);
int hinic_mbox_to_host_sync(void *hwdev, enum hinic_mod_type mod,
u8 cmd, void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
int hinic_mbox_ppf_to_vf(void *hwdev,
enum hinic_mod_type mod, u16 func_id, u8 cmd, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size, u32 timeout);
u8 cmd, void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
int hinic_mbox_ppf_to_vf(void *hwdev, enum hinic_mod_type mod, u16 func_id,
u8 cmd, void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
int hinic_get_card_present_state(void *hwdev, bool *card_present_state);
......
drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h
浏览文件 @ e6a07712
......@@ -533,6 +533,7 @@ struct hinic_micro_log_info {
int (*init)(void *hwdev);
void (*deinit)(void *hwdev);
};
int hinic_register_micro_log(struct hinic_micro_log_info *micro_log_info);
void hinic_unregister_micro_log(struct hinic_micro_log_info *micro_log_info);
......
drivers/net/ethernet/huawei/hinic/hinic_hwdev.c
浏览文件 @ e6a07712
......@@ -47,23 +47,23 @@
#define HINIC_DEAULT_EQ_MSIX_COALESC_TIMER_CFG 0xFF
#define HINIC_DEAULT_EQ_MSIX_RESEND_TIMER_CFG 7
#define HINIC_WAIT_IO_STATUS_TIMEOUT 100
#define HINIC_WAIT_IO_STATUS_TIMEOUT 100
#define HINIC_FLR_TIMEOUT 1000
#define HINIC_FLR_TIMEOUT 1000
#define HINIC_HT_GPA_PAGE_SIZE 4096UL
#define HINIC_HT_GPA_PAGE_SIZE 4096UL
#define HINIC_PPF_HT_GPA_SET_RETRY_TIMES 10
#define HINIC_PPF_HT_GPA_SET_RETRY_TIMES 10
#define HINIC_OK_FLAG_OK 0
#define HINIC_OK_FLAG_FAILED 1
#define HINIC_OK_FLAG_FAILED 1
#define HINIC_GET_SFP_INFO_REAL_TIME 0x1
#define HINIC_GET_SFP_INFO_REAL_TIME 0x1
#define HINIC_GLB_SO_RO_CFG_SHIFT 0x0
#define HINIC_GLB_SO_RO_CFG_MASK 0x1
#define HINIC_DISABLE_ORDER 0
#define HINIC_GLB_SO_RO_CFG_SHIFT 0x0
#define HINIC_GLB_SO_RO_CFG_MASK 0x1
#define HINIC_DISABLE_ORDER 0
#define HINIC_GLB_DMA_SO_RO_GET(val, member) \
(((val) >> HINIC_GLB_##member##_SHIFT) & HINIC_GLB_##member##_MASK)
......@@ -73,10 +73,10 @@
#define HINIC_GLB_DMA_SO_R0_SET(val, member) \
(((val) & HINIC_GLB_##member##_MASK) << HINIC_GLB_##member##_SHIFT)
#define HINIC_MGMT_CHANNEL_STATUS_SHIFT 0x0
#define HINIC_MGMT_CHANNEL_STATUS_MASK 0x1
#define HINIC_ACTIVE_STATUS_MASK 0x80000000
#define HINIC_ACTIVE_STATUS_CLEAR 0x7FFFFFFF
#define HINIC_MGMT_CHANNEL_STATUS_SHIFT 0x0
#define HINIC_MGMT_CHANNEL_STATUS_MASK 0x1
#define HINIC_ACTIVE_STATUS_MASK 0x80000000
#define HINIC_ACTIVE_STATUS_CLEAR 0x7FFFFFFF
#define HINIC_GET_MGMT_CHANNEL_STATUS(val, member) \
(((val) >> HINIC_##member##_SHIFT) & HINIC_##member##_MASK)
......@@ -386,7 +386,7 @@ struct hinic_wq_page_size {
u32 rsvd1;
};
#define MAX_PCIE_DFX_BUF_SIZE (1024)
#define MAX_PCIE_DFX_BUF_SIZE 1024
struct hinic_pcie_dfx_ntc {
u8 status;
......@@ -642,10 +642,11 @@ static void __print_status_info(struct hinic_hwdev *dev,
mod, cmd, mgmt_status_log[index].log);
} else if (mod == HINIC_MOD_L2NIC ||
mod == HINIC_MOD_HILINK) {
if (HINIC_IS_VF(dev) && (cmd == HINIC_PORT_CMD_SET_MAC || cmd ==
HINIC_PORT_CMD_DEL_MAC || cmd ==
HINIC_PORT_CMD_UPDATE_MAC) &&
(mgmt_status_log[index].status == HINIC_PF_SET_VF_ALREADY))
if (HINIC_IS_VF(dev) &&
(cmd == HINIC_PORT_CMD_SET_MAC ||
cmd == HINIC_PORT_CMD_DEL_MAC ||
cmd == HINIC_PORT_CMD_UPDATE_MAC) &&
mgmt_status_log[index].status == HINIC_PF_SET_VF_ALREADY)
return;
nic_err(dev->dev_hdl, "Mgmt process mod(0x%x) cmd(0x%x) fail: %s",
......@@ -694,7 +695,7 @@ static void hinic_print_status_info(void *hwdev, enum hinic_mod_type mod,
if (hinic_status_need_special_handle(mod, cmd, status))
return;
size = sizeof(mgmt_status_log) / sizeof(mgmt_status_log[0]);
size = ARRAY_SIZE(mgmt_status_log);
for (i = 0; i < size; i++) {
if (status == mgmt_status_log[i].status) {
__print_status_info(dev, mod, cmd, i);
......@@ -795,7 +796,8 @@ static int __func_send_mbox(struct hinic_hwdev *hwdev, enum hinic_mod_type mod,
out_size, timeout);
else if (NEED_MBOX_FORWARD(hwdev))
err = hinic_mbox_to_host_sync(hwdev, mod, cmd, buf_in,
in_size, buf_out, out_size, timeout);
in_size, buf_out, out_size,
timeout);
else
err = -EFAULT;
......@@ -1088,8 +1090,7 @@ int hinic_mbox_to_vf(void *hwdev,
EXPORT_SYMBOL(hinic_mbox_to_vf);
int hinic_clp_to_mgmt(void *hwdev, enum hinic_mod_type mod, u8 cmd,
void *buf_in, u16 in_size,
void *buf_out, u16 *out_size)
void *buf_in, u16 in_size, void *buf_out, u16 *out_size)
{
struct hinic_hwdev *dev = hwdev;
......@@ -1108,7 +1109,7 @@ int hinic_clp_to_mgmt(void *hwdev, enum hinic_mod_type mod, u8 cmd,
return -EPERM;
err = hinic_pf_clp_to_mgmt(dev, mod, cmd, buf_in,
in_size, buf_out, out_size);
in_size, buf_out, out_size);
return err;
}
......@@ -1769,8 +1770,8 @@ static int init_ceqs_msix_attr(struct hinic_hwdev *hwdev)
*/
static void set_pf_dma_attr_entry(struct hinic_hwdev *hwdev, u32 entry_idx,
u8 st, u8 at, u8 ph,
enum hinic_pcie_nosnoop no_snooping,
enum hinic_pcie_tph tph_en)
enum hinic_pcie_nosnoop no_snooping,
enum hinic_pcie_tph tph_en)
{
u32 addr, val, dma_attr_entry;
......@@ -1796,8 +1797,8 @@ static void set_pf_dma_attr_entry(struct hinic_hwdev *hwdev, u32 entry_idx,
static int set_vf_dma_attr_entry(struct hinic_hwdev *hwdev, u8 entry_idx,
u8 st, u8 at, u8 ph,
enum hinic_pcie_nosnoop no_snooping,
enum hinic_pcie_tph tph_en)
enum hinic_pcie_nosnoop no_snooping,
enum hinic_pcie_tph tph_en)
{
struct hinic_vf_dma_attr_table attr = {0};
u16 out_size = sizeof(attr);
......@@ -1958,7 +1959,7 @@ int comm_pf_mbox_handler(void *handle, u16 vf_id, u8 cmd, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size)
{
int err = 0;
u8 size = sizeof(hw_cmd_support_vf) / sizeof(hw_cmd_support_vf[0]);
u8 size = ARRAY_SIZE(hw_cmd_support_vf);
if (!hinic_mbox_check_cmd_valid(handle, hw_cmd_support_vf, vf_id, cmd,
buf_in, in_size, size)) {
......@@ -2173,6 +2174,7 @@ static void hinic_comm_pf_to_mgmt_free(struct hinic_hwdev *hwdev)
hinic_pf_to_mgmt_free(hwdev);
}
static int hinic_comm_clp_to_mgmt_init(struct hinic_hwdev *hwdev)
{
int err;
......@@ -2327,7 +2329,6 @@ static int __get_func_misc_info(struct hinic_hwdev *hwdev)
return 0;
}
/* initialize communication channel */
int hinic_init_comm_ch(struct hinic_hwdev *hwdev)
{
......@@ -3289,7 +3290,7 @@ static struct hinic_event_convert __event_convert[] = {
static enum hinic_event_cmd __get_event_type(u8 mod, u8 cmd)
{
int idx;
int arr_size = sizeof(__event_convert) / sizeof(__event_convert[0]);
int arr_size = ARRAY_SIZE(__event_convert);
for (idx = 0; idx < arr_size; idx++) {
if (__event_convert[idx].mod == mod &&
......@@ -4232,6 +4233,7 @@ static int vf_nic_event_handler(void *hwdev, u8 cmd, void *buf_in,
{
enum hinic_event_cmd type = __get_event_type(HINIC_MOD_L2NIC, cmd);
if (type == HINIC_EVENT_MAX_TYPE) {
sdk_warn(((struct hinic_hwdev *)hwdev)->dev_hdl,
"Unsupport L2NIC event: cmd %d\n", cmd);
......@@ -4249,6 +4251,7 @@ static int vf_comm_event_handler(void *hwdev, u8 cmd, void *buf_in,
{
enum hinic_event_cmd type = __get_event_type(HINIC_MOD_COMM, cmd);
if (type == HINIC_EVENT_MAX_TYPE) {
sdk_warn(((struct hinic_hwdev *)hwdev)->dev_hdl,
"Unsupport COMM event: cmd %d\n", cmd);
......@@ -4267,6 +4270,7 @@ static void pf_nic_event_handler(void *hwdev, void *pri_handle, u8 cmd,
void *buf_out, u16 *out_size)
{
enum hinic_event_cmd type = __get_event_type(HINIC_MOD_L2NIC, cmd);
if (type == HINIC_EVENT_MAX_TYPE) {
sdk_warn(((struct hinic_hwdev *)hwdev)->dev_hdl,
"Unsupport L2NIC event: cmd %d\n", cmd);
......@@ -4282,6 +4286,7 @@ static void pf_hilink_event_handler(void *hwdev, void *pri_handle, u8 cmd,
void *buf_out, u16 *out_size)
{
enum hinic_event_cmd type = __get_event_type(HINIC_MOD_HILINK, cmd);
if (type == HINIC_EVENT_MAX_TYPE) {
sdk_warn(((struct hinic_hwdev *)hwdev)->dev_hdl,
"Unsupport HILINK event: cmd %d\n", cmd);
......@@ -4316,7 +4321,7 @@ void mgmt_fmw_act_event_handler(void *hwdev, void *buf_in, u16 in_size,
}
void mgmt_pcie_dfx_event_handler(void *hwdev, void *buf_in, u16 in_size,
void *buf_out, u16 *out_size)
void *buf_out, u16 *out_size)
{
_event_handler(hwdev, HINIC_EVENT_MGMT_PCIE_DFX, buf_in,
in_size, buf_out, out_size);
......@@ -4897,8 +4902,8 @@ int hinic_set_ip_check(void *hwdev, bool ip_check_ctl)
for (i = 0; i <= HINIC_IPSU_CHANNEL_NUM; i++) {
ret = hinic_api_csr_rd32(hwdev, HINIC_NODE_ID_IPSU,
(HINIC_IPSU_CHANNEL0_ADDR +
i * HINIC_IPSU_CHANNEL_OFFSET), &val);
(HINIC_IPSU_CHANNEL0_ADDR +
i * HINIC_IPSU_CHANNEL_OFFSET), &val);
if (ret)
return ret;
......@@ -4910,8 +4915,8 @@ int hinic_set_ip_check(void *hwdev, bool ip_check_ctl)
val = cpu_to_be32(val);
ret = hinic_api_csr_wr32(hwdev, HINIC_NODE_ID_IPSU,
(HINIC_IPSU_CHANNEL0_ADDR +
i * HINIC_IPSU_CHANNEL_OFFSET), val);
(HINIC_IPSU_CHANNEL0_ADDR +
i * HINIC_IPSU_CHANNEL_OFFSET), val);
if (ret)
return ret;
}
......@@ -4957,7 +4962,7 @@ int hinic_set_vxlan_udp_dport(void *hwdev, u32 udp_port)
return 0;
ret = hinic_api_csr_rd32(hwdev, HINIC_NODE_ID_IPSU,
HINIC_IPSURX_VXLAN_DPORT_ADDR, &val);
HINIC_IPSURX_VXLAN_DPORT_ADDR, &val);
if (ret)
return ret;
......@@ -4970,7 +4975,7 @@ int hinic_set_vxlan_udp_dport(void *hwdev, u32 udp_port)
udp_port = cpu_to_be32(udp_port);
ret = hinic_api_csr_wr32(hwdev, HINIC_NODE_ID_IPSU,
HINIC_IPSURX_VXLAN_DPORT_ADDR, udp_port);
HINIC_IPSURX_VXLAN_DPORT_ADDR, udp_port);
if (ret)
return ret;
......
drivers/net/ethernet/huawei/hinic/hinic_hwdev.h
浏览文件 @ e6a07712
......@@ -22,7 +22,7 @@
#define HINIC_DEFAULT_WQ_PAGE_SIZE 0x40000
#define HINIC_HW_WQ_PAGE_SIZE 0x1000
#define HINIC_MSG_TO_MGMT_MAX_LEN 2016
#define HINIC_MSG_TO_MGMT_MAX_LEN 2016
#define HINIC_MGMT_STATUS_ERR_OK 0 /* Ok */
#define HINIC_MGMT_STATUS_ERR_PARAM 1 /* Invalid parameter */
......@@ -48,8 +48,8 @@
#define HINIC_MGMT_STATUS_ERR_LEN 32 /* Length too short or too long */
#define HINIC_MGMT_STATUS_ERR_UNSUPPORT 0xFF /* Feature not supported */
#define HINIC_CHIP_PRESENT 1
#define HINIC_CHIP_ABSENT 0
#define HINIC_CHIP_PRESENT 1
#define HINIC_CHIP_ABSENT 0
struct cfg_mgmt_info;
struct rdma_comp_resource;
......@@ -100,7 +100,7 @@ struct mqm_addr_trans_tbl_info {
#define HINIC_DEV_ACTIVE_FW_TIMEOUT (35 * 1000)
#define HINIC_DEV_BUSY_ACTIVE_FW 0xFE
#define HINIC_HW_WQ_NAME "hinic_hardware"
#define HINIC_HW_WQ_NAME "hinic_hardware"
#define HINIC_HEARTBEAT_PERIOD 1000
#define HINIC_HEARTBEAT_START_EXPIRE 5000
......@@ -224,9 +224,9 @@ struct hinic_hw_stats {
#define HINIC_BOARD_TYPE_MULTI_HOST_ETH_25GE 12
/* new version of roce qp not limited by power of 2 */
#define HINIC_CMD_VER_ROCE_QP 1
#define HINIC_CMD_VER_ROCE_QP 1
/* new version for add function id in multi-host */
#define HINIC_CMD_VER_FUNC_ID 2
#define HINIC_CMD_VER_FUNC_ID 2
struct hinic_hwdev {
void *adapter_hdl; /* pointer to hinic_pcidev or NDIS_Adapter */
......@@ -341,8 +341,8 @@ int hinic_pf_msg_to_mgmt_sync(void *hwdev, enum hinic_mod_type mod, u8 cmd,
void *buf_out, u16 *out_size, u32 timeout);
int hinic_pf_send_clp_cmd(void *hwdev, enum hinic_mod_type mod, u8 cmd,
void *buf_in, u16 in_size,
void *buf_out, u16 *out_size);
void *buf_in, u16 in_size,
void *buf_out, u16 *out_size);
int hinic_get_bios_pf_bw_limit(void *hwdev, u32 *pf_bw_limit);
......@@ -354,8 +354,8 @@ int hinic_set_wq_page_size(struct hinic_hwdev *hwdev, u16 func_idx,
int hinic_phy_init_status_judge(void *hwdev);
int hinic_hilink_info_show(struct hinic_hwdev *hwdev);
extern int hinic_api_csr_rd32(void *hwdev, u8 dest, u32 addr, u32 *val);
extern int hinic_api_csr_wr32(void *hwdev, u8 dest, u32 addr, u32 val);
int hinic_api_csr_rd32(void *hwdev, u8 dest, u32 addr, u32 *val);
int hinic_api_csr_wr32(void *hwdev, u8 dest, u32 addr, u32 val);
int hinic_ppf_process_mbox_msg(struct hinic_hwdev *hwdev, u16 pf_idx, u16 vf_id,
enum hinic_mod_type mod, u8 cmd, void *buf_in,
......
drivers/net/ethernet/huawei/hinic/hinic_hwif.c
浏览文件 @ e6a07712
......@@ -796,7 +796,6 @@ void hinic_func_own_free(void *hwdev)
hinic_func_own_bit_set(dev, 0);
up(&dev->func_sem);
return;
}
/**
......@@ -969,7 +968,7 @@ EXPORT_SYMBOL(hinic_ppf_idx);
#define CEQ_CTRL_0_CHIP_MODE_MASK 0xFU
#define CEQ_CTRL_0_GET(val, member) \
(((val) >> CEQ_CTRL_0_##member##_SHIFT) & \
CEQ_CTRL_0_##member##_MASK)
CEQ_CTRL_0_##member##_MASK)
/**
* hinic_get_db_size - get db size ceq ctrl: bit26~29: uP write vf mode is
......
drivers/net/ethernet/huawei/hinic/hinic_lld.c
浏览文件 @ e6a07712
......@@ -45,10 +45,10 @@
#define SELF_TEST_BAR_ADDR_OFFSET 0x883c
#define HINIC_SECOND_BASE (1000)
#define HINIC_SYNC_YEAR_OFFSET (1900)
#define HINIC_SYNC_MONTH_OFFSET (1)
#define HINIC_MINUTE_BASE (60)
#define HINIC_SECOND_BASE 1000
#define HINIC_SYNC_YEAR_OFFSET 1900
#define HINIC_SYNC_MONTH_OFFSET 1
#define HINIC_MINUTE_BASE 60
#define HINIC_WAIT_TOOL_CNT_TIMEOUT 10000
#define HINIC_WAIT_SRIOV_CFG_TIMEOUT 15000
......@@ -120,6 +120,7 @@ struct hinic_pcidev {
struct timer_list syncfw_time_timer;
};
#define HINIC_EVENT_PROCESS_TIMEOUT 10000
#define FIND_BIT(num, n) (((num) & (1UL << (n))) ? 1 : 0)
......@@ -261,6 +262,7 @@ static int attach_uld(struct hinic_pcidev *dev, enum hinic_service_type type,
{
void *uld_dev = NULL;
int err;
mutex_lock(&dev->pdev_mutex);
if (dev->init_state < HINIC_INIT_STATE_HWDEV_INITED) {
......@@ -1334,8 +1336,6 @@ void hinic_get_card_func_info_by_card_name(const char *chip_name,
}
lld_dev_put();
return;
}
int hinic_get_device_id(void *hwdev, u16 *dev_id)
......@@ -2187,6 +2187,7 @@ static void hinic_set_vf_load_state(struct hinic_pcidev *pci_adapter,
int hinic_ovs_set_vf_load_state(struct pci_dev *pdev)
{
struct hinic_pcidev *pci_adapter;
if (!pdev) {
pr_err("pdev is null\n");
return -EINVAL;
......@@ -2659,12 +2660,10 @@ static void slave_host_init_delay_work(struct work_struct *work)
clear_bit(HINIC_FUNC_PRB_DELAY, &pci_adapter->flag);
if (err)
set_bit(HINIC_FUNC_PRB_ERR, &pci_adapter->flag);
return;
} else {
queue_delayed_work(pci_adapter->slave_nic_init_workq,
&pci_adapter->slave_nic_init_dwork,
HINIC_SLAVE_NIC_DELAY_TIME);
return;
}
}
......@@ -2861,10 +2860,11 @@ static void __exit hinic_lld_exit(void)
pci_unregister_driver(&hinic_driver);
hinic_unregister_uld(SERVICE_T_NIC);
}
module_init(hinic_lld_init);
module_exit(hinic_lld_exit);
int hinic_register_micro_log(struct hinic_micro_log_info *micro_log_info)
{
struct card_node *chip_node;
......
drivers/net/ethernet/huawei/hinic/hinic_lld.h
浏览文件 @ e6a07712
......@@ -16,8 +16,8 @@
#ifndef HINIC_LLD_H_
#define HINIC_LLD_H_
#define HINIC_SLAVE_NIC_DELAY "hinic_slave_nic_delay"
#define HINIC_SLAVE_NIC_DELAY_TIME (5 * HZ)
#define HINIC_SLAVE_NIC_DELAY "hinic_slave_nic_delay"
#define HINIC_SLAVE_NIC_DELAY_TIME (5 * HZ)
struct hinic_lld_dev {
struct pci_dev *pdev;
......
drivers/net/ethernet/huawei/hinic/hinic_main.c
浏览文件 @ e6a07712
......@@ -107,12 +107,10 @@ static unsigned char set_link_status_follow = HINIC_LINK_FOLLOW_STATUS_MAX;
module_param(set_link_status_follow, byte, 0444);
MODULE_PARM_DESC(set_link_status_follow, "Set link status follow port status. 0 - default, 1 - follow, 2 - separate, other - unset. (default unset)");
static unsigned int lro_replenish_thld = 256;
module_param(lro_replenish_thld, uint, 0444);
MODULE_PARM_DESC(lro_replenish_thld, "Number wqe for lro replenish buffer (default=256)");
static bool l2nic_interrupt_switch = true;
module_param(l2nic_interrupt_switch, bool, 0644);
MODULE_PARM_DESC(l2nic_interrupt_switch, "Control whether execute l2nic io interrupt switch or not, default is true");
......@@ -632,9 +630,9 @@ static void __calc_coal_para(struct hinic_nic_dev *nic_dev,
if (nic_dev->in_vm)
*pending_limt = (u8)((rate - q_coal->pkt_rate_low) *
(q_coal->rx_pending_limt_high -
q_coal->rx_pending_limt_low) /
q_coal->rx_pending_limt_low) /
(q_coal->pkt_rate_high -
q_coal->pkt_rate_low) +
q_coal->pkt_rate_low) +
q_coal->rx_pending_limt_low);
else
*pending_limt = q_coal->rx_pending_limt_low;
......@@ -1158,8 +1156,8 @@ static u16 select_queue_by_toeplitz(struct net_device *dev,
}
static u16 hinic_select_queue(struct net_device *netdev, struct sk_buff *skb,
struct net_device *sb_dev,
select_queue_fallback_t fallback)
struct net_device *sb_dev,
select_queue_fallback_t fallback)
{
struct hinic_nic_dev *nic_dev = netdev_priv(netdev);
......@@ -1178,7 +1176,7 @@ static u16 hinic_select_queue(struct net_device *netdev, struct sk_buff *skb,
}
static void hinic_get_stats64(struct net_device *netdev,
struct rtnl_link_stats64 *stats)
struct rtnl_link_stats64 *stats)
{
struct hinic_nic_dev *nic_dev = netdev_priv(netdev);
struct hinic_txq_stats *txq_stats;
......@@ -2131,14 +2129,14 @@ static void netdev_feature_init(struct net_device *netdev)
}
#define MOD_PARA_VALIDATE_NUM_QPS(nic_dev, num_qps, out_qps) { \
if ((num_qps) > nic_dev->max_qps) \
nic_warn(&nic_dev->pdev->dev, \
if ((num_qps) > (nic_dev)->max_qps) \
nic_warn(&(nic_dev)->pdev->dev, \
"Module Parameter %s value %d is out of range, "\
"Maximum value for the device: %d, using %d\n",\
#num_qps, num_qps, nic_dev->max_qps, \
nic_dev->max_qps); \
if (!(num_qps) || (num_qps) > nic_dev->max_qps) \
out_qps = nic_dev->max_qps; \
#num_qps, num_qps, (nic_dev)->max_qps, \
(nic_dev)->max_qps); \
if (!(num_qps) || (num_qps) > (nic_dev)->max_qps) \
out_qps = (nic_dev)->max_qps; \
else \
out_qps = num_qps; \
}
......@@ -2151,7 +2149,6 @@ static void hinic_try_to_enable_rss(struct hinic_nic_dev *nic_dev)
enum hinic_service_mode service_mode =
hinic_get_service_mode(nic_dev->hwdev);
nic_dev->max_qps = hinic_func_max_nic_qnum(nic_dev->hwdev);
if (nic_dev->max_qps <= 1) {
clear_bit(HINIC_RSS_ENABLE, &nic_dev->flags);
......@@ -2733,7 +2730,6 @@ static int nic_probe(struct hinic_lld_dev *lld_dev, void **uld_dev,
return -ENOMEM;
}
SET_NETDEV_DEV(netdev, &pdev->dev);
nic_dev = (struct hinic_nic_dev *)netdev_priv(netdev);
nic_dev->hwdev = lld_dev->hwdev;
......@@ -2749,7 +2745,6 @@ static int nic_probe(struct hinic_lld_dev *lld_dev, void **uld_dev,
page_num = (RX_BUFF_NUM_PER_PAGE * nic_dev->rx_buff_len) / PAGE_SIZE;
nic_dev->page_order = page_num > 0 ? ilog2(page_num) : 0;
mutex_init(&nic_dev->nic_mutex);
adaptive_configuration_init(nic_dev);
......
drivers/net/ethernet/huawei/hinic/hinic_mbox.c
浏览文件 @ e6a07712
......@@ -52,7 +52,7 @@
#define HINIC_MBOX_INT_SET(val, field) \
(((val) & HINIC_MBOX_INT_##field##_MASK) << \
HINIC_MBOX_INT_##field##_SHIFT)
HINIC_MBOX_INT_##field##_SHIFT)
enum hinic_mbox_tx_status {
TX_NOT_DONE = 1,
......@@ -70,7 +70,7 @@ enum hinic_mbox_tx_status {
#define HINIC_MBOX_CTRL_SET(val, field) \
(((val) & HINIC_MBOX_CTRL_##field##_MASK) << \
HINIC_MBOX_CTRL_##field##_SHIFT)
HINIC_MBOX_CTRL_##field##_SHIFT)
#define HINIC_MBOX_HEADER_MSG_LEN_SHIFT 0
#define HINIC_MBOX_HEADER_MODULE_SHIFT 11
......@@ -102,10 +102,10 @@ enum hinic_mbox_tx_status {
#define HINIC_MBOX_HEADER_GET(val, field) \
(((val) >> HINIC_MBOX_HEADER_##field##_SHIFT) & \
HINIC_MBOX_HEADER_##field##_MASK)
HINIC_MBOX_HEADER_##field##_MASK)
#define HINIC_MBOX_HEADER_SET(val, field) \
((u64)((val) & HINIC_MBOX_HEADER_##field##_MASK) << \
HINIC_MBOX_HEADER_##field##_SHIFT)
HINIC_MBOX_HEADER_##field##_SHIFT)
#define MBOX_SEGLEN_MASK \
HINIC_MBOX_HEADER_SET(HINIC_MBOX_HEADER_SEG_LEN_MASK, SEG_LEN)
......@@ -395,7 +395,7 @@ void hinic_unregister_vf_mbox_cb(struct hinic_hwdev *hwdev,
clear_bit(HINIC_VF_MBOX_CB_REG, &func_to_func->vf_mbox_cb_state[mod]);
while (test_bit(HINIC_VF_MBOX_CB_RUNNING,
&func_to_func->vf_mbox_cb_state[mod]))
&func_to_func->vf_mbox_cb_state[mod]))
usleep_range(900, 1000);
func_to_func->vf_mbox_cb[mod] = NULL;
......@@ -671,8 +671,8 @@ static bool check_mbox_seq_id_and_seg_len(struct hinic_recv_mbox *recv_mbox,
} else {
if (seq_id != recv_mbox->seq_id + 1)
return false;
else
recv_mbox->seq_id = seq_id;
recv_mbox->seq_id = seq_id;
}
return true;
......@@ -1448,9 +1448,9 @@ int __hinic_mbox_to_vf(void *hwdev,
in_size, buf_out, out_size, timeout);
}
int hinic_mbox_ppf_to_vf(void *hwdev,
enum hinic_mod_type mod, u16 func_id, u8 cmd, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size, u32 timeout)
int hinic_mbox_ppf_to_vf(void *hwdev, enum hinic_mod_type mod, u16 func_id,
u8 cmd, void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout)
{
struct hinic_mbox_func_to_func *func_to_func;
int err;
......@@ -1620,7 +1620,8 @@ int hinic_vf_mbox_random_id_init(struct hinic_hwdev *hwdev)
for (vf_in_pf = 1; vf_in_pf <= hinic_func_max_vf(hwdev); vf_in_pf++) {
err = set_vf_mbox_random_id(hwdev,
(hinic_glb_pf_vf_offset(hwdev) + vf_in_pf));
hinic_glb_pf_vf_offset(hwdev) +
vf_in_pf);
if (err)
break;
}
......
drivers/net/ethernet/huawei/hinic/hinic_mbox.h
浏览文件 @ e6a07712
......@@ -221,12 +221,12 @@ int hinic_mbox_to_pf_no_ack(struct hinic_hwdev *hwdev, enum hinic_mod_type mod,
int hinic_mbox_ppf_to_pf(struct hinic_hwdev *hwdev, enum hinic_mod_type mod,
u16 dst_pf_id, u8 cmd,
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
int hinic_mbox_to_func(struct hinic_mbox_func_to_func *func_to_func,
enum hinic_mod_type mod, u16 cmd, u16 dst_func,
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
enum hinic_mod_type mod, u16 cmd, u16 dst_func,
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
int __hinic_mbox_to_vf(void *hwdev,
enum hinic_mod_type mod, u16 vf_id, u8 cmd, void *buf_in,
......
drivers/net/ethernet/huawei/hinic/hinic_mgmt.c
浏览文件 @ e6a07712
......@@ -62,11 +62,11 @@
#define MAX_MSG_SZ 2016
#define MAX_CMD_BUF_SIZE 2048ULL
#define MAX_CMD_BUF_SIZE 2048ULL
#define MSG_SZ_IS_VALID(in_size) ((in_size) <= MAX_MSG_SZ)
#define SYNC_MSG_ID(pf_to_mgmt) ((pf_to_mgmt)->sync_msg_id)
#define SYNC_MSG_ID(pf_to_mgmt) ((pf_to_mgmt)->sync_msg_id)
#define SYNC_MSG_ID_INC(pf_to_mgmt) (SYNC_MSG_ID(pf_to_mgmt) = \
(SYNC_MSG_ID(pf_to_mgmt) + 1) & SYNC_MSG_ID_MASK)
......@@ -251,10 +251,11 @@ static void prepare_header(struct hinic_msg_pf_to_mgmt *pf_to_mgmt,
}
static void clp_prepare_header(struct hinic_hwdev *hwdev,
u64 *header, u16 msg_len, enum hinic_mod_type mod,
enum hinic_msg_ack_type ack_type,
enum hinic_msg_direction_type direction,
enum hinic_mgmt_cmd cmd, u32 msg_id)
u64 *header, u16 msg_len,
enum hinic_mod_type mod,
enum hinic_msg_ack_type ack_type,
enum hinic_msg_direction_type direction,
enum hinic_mgmt_cmd cmd, u32 msg_id)
{
struct hinic_hwif *hwif = hwdev->hwif;
......@@ -304,9 +305,9 @@ static void prepare_mgmt_cmd(u8 *mgmt_cmd, u64 *header, const void *msg,
*/
static int send_msg_to_mgmt_async(struct hinic_msg_pf_to_mgmt *pf_to_mgmt,
enum hinic_mod_type mod, u8 cmd,
void *msg, u16 msg_len,
enum hinic_msg_direction_type direction,
u16 resp_msg_id)
void *msg, u16 msg_len,
enum hinic_msg_direction_type direction,
u16 resp_msg_id)
{
void *mgmt_cmd = pf_to_mgmt->async_msg_buf;
struct hinic_api_cmd_chain *chain;
......@@ -331,7 +332,7 @@ static int send_msg_to_mgmt_async(struct hinic_msg_pf_to_mgmt *pf_to_mgmt,
chain = pf_to_mgmt->cmd_chain[HINIC_API_CMD_WRITE_ASYNC_TO_MGMT_CPU];
return hinic_api_cmd_write(chain, HINIC_NODE_ID_MGMT_HOST, mgmt_cmd,
cmd_size);
cmd_size);
}
int hinic_pf_to_mgmt_async(void *hwdev, enum hinic_mod_type mod,
......@@ -373,10 +374,10 @@ int hinic_pf_to_mgmt_async(void *hwdev, enum hinic_mod_type mod,
*/
static int send_msg_to_mgmt_sync(struct hinic_msg_pf_to_mgmt *pf_to_mgmt,
enum hinic_mod_type mod, u8 cmd,
void *msg, u16 msg_len,
enum hinic_msg_ack_type ack_type,
enum hinic_msg_direction_type direction,
u16 resp_msg_id)
void *msg, u16 msg_len,
enum hinic_msg_ack_type ack_type,
enum hinic_msg_direction_type direction,
u16 resp_msg_id)
{
void *mgmt_cmd = pf_to_mgmt->sync_msg_buf;
struct hinic_api_cmd_chain *chain;
......@@ -486,7 +487,7 @@ int hinic_pf_to_mgmt_sync(void *hwdev, enum hinic_mod_type mod, u8 cmd,
}
static int __get_clp_reg(void *hwdev, enum clp_data_type data_type,
enum clp_reg_type reg_type, u32 *reg_addr)
enum clp_reg_type reg_type, u32 *reg_addr)
{
struct hinic_hwdev *dev = hwdev;
u32 offset;
......@@ -530,8 +531,8 @@ static int __get_clp_reg(void *hwdev, enum clp_data_type data_type,
}
static int hinic_read_clp_reg(struct hinic_hwdev *hwdev,
enum clp_data_type data_type,
enum clp_reg_type reg_type, u32 *read_value)
enum clp_data_type data_type,
enum clp_reg_type reg_type, u32 *read_value)
{
int err;
u32 reg_addr, reg_value;
......@@ -660,7 +661,7 @@ static void hinic_write_clp_reg(struct hinic_hwdev *hwdev,
}
static int hinic_read_clp_data(struct hinic_hwdev *hwdev,
void *buf_out, u16 *out_size)
void *buf_out, u16 *out_size)
{
int err;
u32 reg = HINIC_CLP_DATA(RSP);
......@@ -788,7 +789,7 @@ static int hinic_check_clp_init_status(struct hinic_hwdev *hwdev)
}
static void hinic_clear_clp_data(struct hinic_hwdev *hwdev,
enum clp_data_type data_type)
enum clp_data_type data_type)
{
u32 reg = (data_type == HINIC_CLP_REQ_HOST) ?
HINIC_CLP_DATA(REQ) : HINIC_CLP_DATA(RSP);
......@@ -801,8 +802,8 @@ static void hinic_clear_clp_data(struct hinic_hwdev *hwdev,
}
int hinic_pf_clp_to_mgmt(void *hwdev, enum hinic_mod_type mod, u8 cmd,
const void *buf_in, u16 in_size,
void *buf_out, u16 *out_size)
const void *buf_in, u16 in_size,
void *buf_out, u16 *out_size)
{
struct hinic_clp_pf_to_mgmt *clp_pf_to_mgmt;
struct hinic_hwdev *dev = hwdev;
......
drivers/net/ethernet/huawei/hinic/hinic_mgmt.h
浏览文件 @ e6a07712
......@@ -44,18 +44,19 @@
#define HINIC_MSG_HEADER_GET(val, member) \
(((val) >> HINIC_MSG_HEADER_##member##_SHIFT) & \
HINIC_MSG_HEADER_##member##_MASK)
HINIC_MSG_HEADER_##member##_MASK)
#define HINIC_MSG_HEADER_SET(val, member) \
((u64)((val) & HINIC_MSG_HEADER_##member##_MASK) << \
HINIC_MSG_HEADER_##member##_SHIFT)
HINIC_MSG_HEADER_##member##_SHIFT)
#define HINIC_MGMT_WQ_NAME "hinic_mgmt"
#define HINIC_MGMT_WQ_NAME "hinic_mgmt"
enum clp_data_type {
HINIC_CLP_REQ_HOST = 0,
HINIC_CLP_RSP_HOST = 1
};
enum clp_reg_type {
HINIC_CLP_BA_HOST = 0,
HINIC_CLP_SIZE_HOST = 1,
......@@ -63,12 +64,13 @@ enum clp_reg_type {
HINIC_CLP_START_REQ_HOST = 3,
HINIC_CLP_READY_RSP_HOST = 4
};
#define HINIC_CLP_REG_GAP (0x20)
#define HINIC_CLP_INPUT_BUFFER_LEN_HOST (4096UL)
#define HINIC_CLP_DATA_UNIT_HOST (4UL)
#define HINIC_BAR01_GLOABAL_CTL_OFFSET (0x4000)
#define HINIC_BAR01_CLP_OFFSET (0x5000)
#define HINIC_CLP_REG_GAP 0x20
#define HINIC_CLP_INPUT_BUFFER_LEN_HOST 4096UL
#define HINIC_CLP_DATA_UNIT_HOST 4UL
#define HINIC_BAR01_GLOABAL_CTL_OFFSET 0x4000
#define HINIC_BAR01_CLP_OFFSET 0x5000
#define HINIC_CLP_SRAM_SIZE_REG (HINIC_BAR01_GLOABAL_CTL_OFFSET + 0x220)
#define HINIC_CLP_REQ_SRAM_BA_REG (HINIC_BAR01_GLOABAL_CTL_OFFSET + 0x224)
......@@ -77,29 +79,29 @@ enum clp_reg_type {
#define HINIC_CLP_RSP_REG (HINIC_BAR01_GLOABAL_CTL_OFFSET + 0x230)
#define HINIC_CLP_REG(member) (HINIC_CLP_##member##_REG)
#define HINIC_CLP_REQ_DATA (HINIC_BAR01_CLP_OFFSET)
#define HINIC_CLP_REQ_DATA (HINIC_BAR01_CLP_OFFSET)
#define HINIC_CLP_RSP_DATA (HINIC_BAR01_CLP_OFFSET + 0x1000)
#define HINIC_CLP_DATA(member) (HINIC_CLP_##member##_DATA)
#define HINIC_CLP_DATA(member) (HINIC_CLP_##member##_DATA)
#define HINIC_CLP_SRAM_SIZE_OFFSET (16)
#define HINIC_CLP_SRAM_BASE_OFFSET (0)
#define HINIC_CLP_LEN_OFFSET (0)
#define HINIC_CLP_START_OFFSET (31)
#define HINIC_CLP_READY_OFFSET (31)
#define HINIC_CLP_SRAM_SIZE_OFFSET 16
#define HINIC_CLP_SRAM_BASE_OFFSET 0
#define HINIC_CLP_LEN_OFFSET 0
#define HINIC_CLP_START_OFFSET 31
#define HINIC_CLP_READY_OFFSET 31
#define HINIC_CLP_OFFSET(member) (HINIC_CLP_##member##_OFFSET)
#define HINIC_CLP_SRAM_SIZE_BIT_LEN (0x7ffUL)
#define HINIC_CLP_SRAM_BASE_BIT_LEN (0x7ffffffUL)
#define HINIC_CLP_LEN_BIT_LEN (0x7ffUL)
#define HINIC_CLP_START_BIT_LEN (0x1UL)
#define HINIC_CLP_READY_BIT_LEN (0x1UL)
#define HINIC_CLP_SRAM_SIZE_BIT_LEN 0x7ffUL
#define HINIC_CLP_SRAM_BASE_BIT_LEN 0x7ffffffUL
#define HINIC_CLP_LEN_BIT_LEN 0x7ffUL
#define HINIC_CLP_START_BIT_LEN 0x1UL
#define HINIC_CLP_READY_BIT_LEN 0x1UL
#define HINIC_CLP_MASK(member) (HINIC_CLP_##member##_BIT_LEN)
#define HINIC_CLP_DELAY_CNT_MAX (200UL)
#define HINIC_CLP_SRAM_SIZE_REG_MAX (0x3ff)
#define HINIC_CLP_SRAM_BASE_REG_MAX (0x7ffffff)
#define HINIC_CLP_LEN_REG_MAX (0x3ff)
#define HINIC_CLP_START_OR_READY_REG_MAX (0x1)
#define HINIC_CLP_DELAY_CNT_MAX 200UL
#define HINIC_CLP_SRAM_SIZE_REG_MAX 0x3ff
#define HINIC_CLP_SRAM_BASE_REG_MAX 0x7ffffff
#define HINIC_CLP_LEN_REG_MAX 0x3ff
#define HINIC_CLP_START_OR_READY_REG_MAX 0x1
enum hinic_msg_direction_type {
HINIC_MSG_DIRECT_SEND = 0,
......@@ -228,14 +230,14 @@ void hinic_pf_to_mgmt_free(struct hinic_hwdev *hwdev);
int hinic_pf_to_mgmt_sync(void *hwdev, enum hinic_mod_type mod, u8 cmd,
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size, u32 timeout);
u16 *out_size, u32 timeout);
int hinic_pf_to_mgmt_async(void *hwdev, enum hinic_mod_type mod,
u8 cmd, void *buf_in, u16 in_size);
int hinic_pf_clp_to_mgmt(void *hwdev, enum hinic_mod_type mod, u8 cmd,
const void *buf_in, u16 in_size,
void *buf_out, u16 *out_size);
const void *buf_in, u16 in_size,
void *buf_out, u16 *out_size);
int hinic_clp_pf_to_mgmt_init(struct hinic_hwdev *hwdev);
void hinic_clp_pf_to_mgmt_free(struct hinic_hwdev *hwdev);
......
drivers/net/ethernet/huawei/hinic/hinic_mgmt_interface.h
浏览文件 @ e6a07712
......@@ -939,10 +939,12 @@ struct hinic_link_ksettings_info {
u8 fec; /* 0 - RSFEC; 1 - BASEFEC; 2 - NOFEC */
u8 rsvd2[18]; /* reserved for duplex, port, etc. */
};
enum hinic_tx_promsic {
HINIC_TX_PROMISC_ENABLE = 0,
HINIC_TX_PROMISC_DISABLE = 1,
};
struct hinic_promsic_info {
u8 status;
u8 version;
......
drivers/net/ethernet/huawei/hinic/hinic_msix_attr.c
浏览文件 @ e6a07712
......@@ -74,8 +74,8 @@ int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
*/
int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
u8 *pending_limit, u8 *coalesc_timer_cfg,
u8 *lli_timer_cfg, u8 *lli_credit_limit,
u8 *resend_timer_cfg)
u8 *lli_timer_cfg, u8 *lli_credit_limit,
u8 *resend_timer_cfg)
{
u32 addr, val;
......@@ -108,8 +108,8 @@ int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
*/
int hinic_msix_attr_cnt_set(struct hinic_hwif *hwif, u16 msix_index,
u8 lli_timer_cnt, u8 lli_credit_cnt,
u8 coalesc_timer_cnt, u8 pending_cnt,
u8 resend_timer_cnt)
u8 coalesc_timer_cnt, u8 pending_cnt,
u8 resend_timer_cnt)
{
u32 msix_ctrl, addr;
......
drivers/net/ethernet/huawei/hinic/hinic_msix_attr.h
浏览文件 @ e6a07712
......@@ -29,12 +29,12 @@
#define HINIC_MSIX_RESEND_TIMER_MASK 0x7U
#define HINIC_MSIX_ATTR_GET(val, member) \
(((val) >> HINIC_MSIX_##member##_SHIFT) \
& HINIC_MSIX_##member##_MASK)
(((val) >> HINIC_MSIX_##member##_SHIFT) \
& HINIC_MSIX_##member##_MASK)
#define HINIC_MSIX_ATTR_SET(val, member) \
(((val) & HINIC_MSIX_##member##_MASK) \
<< HINIC_MSIX_##member##_SHIFT)
(((val) & HINIC_MSIX_##member##_MASK) \
<< HINIC_MSIX_##member##_SHIFT)
#define HINIC_MSIX_CNT_LLI_TIMER_SHIFT 0
#define HINIC_MSIX_CNT_LLI_CREDIT_SHIFT 8
......@@ -50,20 +50,20 @@
#define HINIC_MSIX_CNT_SET(val, member) \
(((val) & HINIC_MSIX_CNT_##member##_MASK) << \
HINIC_MSIX_CNT_##member##_SHIFT)
HINIC_MSIX_CNT_##member##_SHIFT)
int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index,
u8 pending_limit, u8 coalesc_timer,
u8 lli_timer_cfg, u8 lli_credit_limit,
u8 resend_timer);
u8 lli_timer_cfg, u8 lli_credit_limit,
u8 resend_timer);
int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index,
u8 *pending_limit, u8 *coalesc_timer_cfg,
u8 *lli_timer_cfg, u8 *lli_credit_limit,
u8 *resend_timer_cfg);
u8 *lli_timer_cfg, u8 *lli_credit_limit,
u8 *resend_timer_cfg);
int hinic_msix_attr_cnt_set(struct hinic_hwif *hwif, u16 msix_index,
u8 pending_limit, u8 coalesc_timer,
u8 lli_timer_cfg, u8 lli_credit_limit,
u8 resend_timer);
u8 lli_timer_cfg, u8 lli_credit_limit,
u8 resend_timer);
#endif
drivers/net/ethernet/huawei/hinic/hinic_multi_host_mgmt.c
浏览文件 @ e6a07712
......@@ -450,7 +450,8 @@ static int multi_host_event_handler(struct hinic_hwdev *hwdev,
}
static int sw_fwd_msg_to_vf(struct hinic_hwdev *hwdev,
void *buf_in, u16 in_size, void *buf_out, u16 *out_size)
void *buf_in, u16 in_size, void *buf_out,
u16 *out_size)
{
struct hinic_host_fwd_head *fwd_head;
u16 fwd_head_len;
......@@ -461,9 +462,9 @@ static int sw_fwd_msg_to_vf(struct hinic_hwdev *hwdev,
fwd_head_len = sizeof(struct hinic_host_fwd_head);
msg = (void *)((u8 *)buf_in + fwd_head_len);
err = hinic_mbox_ppf_to_vf(hwdev, fwd_head->mod,
fwd_head->dst_glb_func_idx, fwd_head->cmd,
msg, (in_size - fwd_head_len),
buf_out, out_size, 0);
fwd_head->dst_glb_func_idx, fwd_head->cmd,
msg, in_size - fwd_head_len,
buf_out, out_size, 0);
if (err)
nic_err(hwdev->dev_hdl,
"Fwd msg to func %u failed, err: %d\n",
......@@ -471,6 +472,7 @@ static int sw_fwd_msg_to_vf(struct hinic_hwdev *hwdev,
return err;
}
static int __slave_host_sw_func_handler(struct hinic_hwdev *hwdev, u16 pf_idx,
u8 cmd, void *buf_in, u16 in_size,
void *buf_out, u16 *out_size)
......@@ -505,7 +507,7 @@ static int __slave_host_sw_func_handler(struct hinic_hwdev *hwdev, u16 pf_idx,
case HINIC_SW_CMD_SEND_MSG_TO_VF:
err = sw_fwd_msg_to_vf(hwdev, buf_in, in_size,
buf_out, out_size);
buf_out, out_size);
break;
case HINIC_SW_CMD_MIGRATE_READY:
......@@ -550,7 +552,8 @@ int __ppf_process_mbox_msg(struct hinic_hwdev *hwdev, u16 pf_idx, u16 vf_id,
if (IS_SLAVE_HOST(hwdev)) {
err = hinic_mbox_to_host_sync(hwdev, mod, cmd,
buf_in, in_size, buf_out, out_size, 0);
buf_in, in_size, buf_out,
out_size, 0);
if (err)
sdk_err(hwdev->dev_hdl, "send to mpf failed, err: %d\n",
err);
......
drivers/net/ethernet/huawei/hinic/hinic_nic_cfg.c
浏览文件 @ e6a07712
......@@ -49,7 +49,7 @@ MODULE_PARM_DESC(set_vf_link_state, "Set vf link state, 0 represents link auto,
hinic_msg_to_mgmt_async(hwdev, HINIC_MOD_L2NIC, cmd, buf_in, in_size)
#define CPATH_FUNC_ID_VALID_LIMIT 2
#define CHECK_IPSU_15BIT 0X8000
#define CHECK_IPSU_15BIT 0X8000
static int hinic_set_rx_lro_timer(void *hwdev, u32 timer_value);
......@@ -256,9 +256,9 @@ int hinic_set_mac(void *hwdev, const u8 *mac_addr, u16 vlan_id, u16 func_id)
sizeof(mac_info), &mac_info, &out_size);
if (err || !out_size ||
(mac_info.status && mac_info.status != HINIC_MGMT_STATUS_EXIST &&
mac_info.status != HINIC_PF_SET_VF_ALREADY) ||
mac_info.status != HINIC_PF_SET_VF_ALREADY) ||
(mac_info.vlan_id & CHECK_IPSU_15BIT &&
mac_info.status == HINIC_MGMT_STATUS_EXIST)) {
mac_info.status == HINIC_MGMT_STATUS_EXIST)) {
nic_err(nic_hwdev->dev_hdl,
"Failed to update MAC, err: %d, status: 0x%x, out size: 0x%x\n",
err, mac_info.status, out_size);
......@@ -344,9 +344,9 @@ int hinic_update_mac(void *hwdev, u8 *old_mac, u8 *new_mac, u16 vlan_id,
&mac_info, &out_size);
if (err || !out_size ||
(mac_info.status && mac_info.status != HINIC_MGMT_STATUS_EXIST &&
mac_info.status != HINIC_PF_SET_VF_ALREADY) ||
mac_info.status != HINIC_PF_SET_VF_ALREADY) ||
(mac_info.vlan_id & CHECK_IPSU_15BIT &&
mac_info.status == HINIC_MGMT_STATUS_EXIST)) {
mac_info.status == HINIC_MGMT_STATUS_EXIST)) {
nic_err(nic_hwdev->dev_hdl,
"Failed to update MAC, err: %d, status: 0x%x, out size: 0x%x\n",
err, mac_info.status, out_size);
......@@ -711,7 +711,7 @@ int hinic_del_vlan(void *hwdev, u16 vlan_id, u16 func_id)
err = l2nic_msg_to_mgmt_sync(hwdev, HINIC_PORT_CMD_DEL_VLAN,
&vlan_info, sizeof(vlan_info),
&vlan_info, &out_size);
&vlan_info, &out_size);
if (err || !out_size || vlan_info.status) {
nic_err(nic_hwdev->dev_hdl,
"Failed to delte vlan, err: %d, status: 0x%x, out size: 0x%x\n",
......@@ -2584,7 +2584,7 @@ static void hinic_get_vf_cos_msg_handler(struct hinic_nic_io *nic_io,
int nic_pf_mbox_handler(void *hwdev, u16 vf_id, u8 cmd, void *buf_in,
u16 in_size, void *buf_out, u16 *out_size)
{
u8 size = sizeof(nic_cmd_support_vf) / sizeof(nic_cmd_support_vf[0]);
u8 size = ARRAY_SIZE(nic_cmd_support_vf);
struct hinic_nic_io *nic_io;
int err = 0;
u32 timeout = 0;
......@@ -3819,6 +3819,7 @@ int hinic_set_link_settings(void *hwdev, struct hinic_link_ksettings *settings)
return info.status;
}
int hinic_disable_tx_promisc(void *hwdev)
{
struct hinic_promsic_info info = {0};
......
drivers/net/ethernet/huawei/hinic/hinic_nic_cfg.h
浏览文件 @ e6a07712
......@@ -41,20 +41,20 @@
#define HINIC_MIN_MTU_SIZE 256
#define HINIC_MAX_JUMBO_FRAME_SIZE 9600
#define HINIC_LRO_MAX_WQE_NUM_UPPER 32
#define HINIC_LRO_MAX_WQE_NUM_LOWER 1
#define HINIC_LRO_MAX_WQE_NUM_DEFAULT_ARM 4
#define HINIC_LRO_MAX_WQE_NUM_DEFAULT_X86 8
#define HINIC_LRO_MAX_WQE_NUM_DEFAULT 8
#define HINIC_LRO_MAX_WQE_NUM_UPPER 32
#define HINIC_LRO_MAX_WQE_NUM_LOWER 1
#define HINIC_LRO_MAX_WQE_NUM_DEFAULT_ARM 4
#define HINIC_LRO_MAX_WQE_NUM_DEFAULT_X86 8
#define HINIC_LRO_MAX_WQE_NUM_DEFAULT 8
#define HINIC_LRO_WQE_NUM_PANGEA_DEFAULT 32
#define HINIC_LRO_RX_TIMER_UPPER 1024
#define HINIC_LRO_RX_TIMER_LOWER 1
#define HINIC_LRO_RX_TIMER_DEFAULT 16
#define HINIC_LRO_RX_TIMER_DEFAULT_25GE 16
#define HINIC_LRO_RX_TIMER_DEFAULT_100GE 64
#define HINIC_LRO_RX_TIMER_UPPER 1024
#define HINIC_LRO_RX_TIMER_LOWER 1
#define HINIC_LRO_RX_TIMER_DEFAULT 16
#define HINIC_LRO_RX_TIMER_DEFAULT_25GE 16
#define HINIC_LRO_RX_TIMER_DEFAULT_100GE 64
#define HINIC_LRO_RX_TIMER_DEFAULT_PG_10GE 10
#define HINIC_LRO_RX_TIMER_DEFAULT_PG_100GE 8
#define HINIC_LRO_RX_TIMER_DEFAULT_PG_100GE 8
#if defined(__aarch64__)
#define HINIC_LOWEST_LATENCY 1
......@@ -83,7 +83,7 @@
#endif
enum hinic_board_type {
HINIC_BOARD_UNKNOWN = 0,
HINIC_BOARD_UNKNOWN = 0,
HINIC_BOARD_10GE = 1,
HINIC_BOARD_25GE = 2,
HINIC_BOARD_40GE = 3,
......@@ -94,13 +94,13 @@ enum hinic_board_type {
};
enum hinic_os_type {
HINIC_OS_UNKNOWN = 0,
HINIC_OS_UNKNOWN = 0,
HINIC_OS_HUAWEI = 1,
HINIC_OS_NON_HUAWEI = 2,
};
enum hinic_cpu_type {
HINIC_CPU_UNKNOWN = 0,
HINIC_CPU_UNKNOWN = 0,
HINIC_CPU_X86_GENERIC = 1,
HINIC_CPU_ARM_GENERIC = 2,
};
......@@ -387,7 +387,7 @@ struct hinic_rq_filter_info {
#define HINIC_MGMT_VERSION_MAX_LEN 32
#define HINIC_FW_VERSION_NAME 16
#define HINIC_FW_VERSION_NAME 16
#define HINIC_FW_VERSION_SECTION_CNT 4
#define HINIC_FW_VERSION_SECTION_BORDER 0xFF
struct hinic_fw_version {
......@@ -627,9 +627,9 @@ int hinic_set_link_settings(void *hwdev, struct hinic_link_ksettings *settings);
int hinic_enable_netq(void *hwdev, u8 en);
int hinic_add_hw_rqfilter(void *hwdev,
struct hinic_rq_filter_info *filter_info);
struct hinic_rq_filter_info *filter_info);
int hinic_del_hw_rqfilter(void *hwdev,
struct hinic_rq_filter_info *filter_info);
struct hinic_rq_filter_info *filter_info);
int hinic_get_sfp_eeprom(void *hwdev, u8 *data, u16 *len);
int hinic_get_sfp_type(void *hwdev, u8 *data0, u8 *data1);
......
drivers/net/ethernet/huawei/hinic/hinic_nic_dbg.c
浏览文件 @ e6a07712
......@@ -31,7 +31,7 @@
#include "hinic_nic.h"
#include "hinic_dbg.h"
#define INVALID_PI (0xFFFF)
#define INVALID_PI 0xFFFF
u16 hinic_dbg_get_qp_num(void *hwdev)
{
......
drivers/net/ethernet/huawei/hinic/hinic_nic_dev.h
浏览文件 @ e6a07712
......@@ -134,11 +134,11 @@ struct hinic_intr_coal_info {
u8 user_set_intr_coal_flag;
};
#define HINIC_NIC_STATS_INC(nic_dev, field) \
{ \
u64_stats_update_begin(&nic_dev->stats.syncp); \
nic_dev->stats.field++; \
u64_stats_update_end(&nic_dev->stats.syncp); \
#define HINIC_NIC_STATS_INC(nic_dev, field) \
{ \
u64_stats_update_begin(&(nic_dev)->stats.syncp); \
(nic_dev)->stats.field++; \
u64_stats_update_end(&(nic_dev)->stats.syncp); \
}
struct hinic_nic_stats {
......@@ -268,12 +268,12 @@ int hinic_enable_func_rss(struct hinic_nic_dev *nic_dev);
#define hinic_msg(level, nic_dev, msglvl, format, arg...) \
do { \
if (nic_dev->netdev && nic_dev->netdev->reg_state \
if ((nic_dev)->netdev && (nic_dev)->netdev->reg_state \
== NETREG_REGISTERED) \
nicif_##level(nic_dev, msglvl, nic_dev->netdev, \
nicif_##level((nic_dev), msglvl, (nic_dev)->netdev, \
format, ## arg); \
else \
nic_##level(&nic_dev->pdev->dev, \
nic_##level(&(nic_dev)->pdev->dev, \
format, ## arg); \
} while (0)
......
drivers/net/ethernet/huawei/hinic/hinic_nic_io.c
浏览文件 @ e6a07712
......@@ -545,9 +545,9 @@ static int init_sq_ctxts(struct hinic_nic_io *nic_io)
cmd_buf->size = SQ_CTXT_SIZE(max_ctxts);
err = hinic_cmdq_direct_resp(hwdev, HINIC_ACK_TYPE_CMDQ,
HINIC_MOD_L2NIC,
HINIC_MOD_L2NIC,
HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT,
cmd_buf, &out_param, 0);
cmd_buf, &out_param, 0);
if (err || out_param != 0) {
nic_err(hwdev->dev_hdl, "Failed to set SQ ctxts, err: %d, out_param: 0x%llx\n",
err, out_param);
......@@ -602,9 +602,9 @@ static int init_rq_ctxts(struct hinic_nic_io *nic_io)
cmd_buf->size = RQ_CTXT_SIZE(max_ctxts);
err = hinic_cmdq_direct_resp(hwdev, HINIC_ACK_TYPE_CMDQ,
HINIC_MOD_L2NIC,
HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT,
cmd_buf, &out_param, 0);
HINIC_MOD_L2NIC,
HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT,
cmd_buf, &out_param, 0);
if (err || out_param != 0) {
nic_err(hwdev->dev_hdl, "Failed to set RQ ctxts, err: %d, out_param: 0x%llx\n",
......@@ -676,8 +676,8 @@ static int clean_queue_offload_ctxt(struct hinic_nic_io *nic_io,
err = hinic_cmdq_direct_resp(hwdev, HINIC_ACK_TYPE_CMDQ,
HINIC_MOD_L2NIC,
HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
cmd_buf, &out_param, 0);
HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
cmd_buf, &out_param, 0);
if ((err) || (out_param)) {
nic_err(hwdev->dev_hdl, "Failed to clean queue offload ctxts, err: %d, out_param: 0x%llx\n",
......
drivers/net/ethernet/huawei/hinic/hinic_nictool.c
浏览文件 @ e6a07712
......@@ -36,8 +36,8 @@
#define HIADM_DEV_CLASS "nictool_class"
#define HIADM_DEV_NAME "nictool_dev"
#define HINIC_CMDQ_BUF_MAX_SIZE 2048U
#define MSG_MAX_IN_SIZE (2048 * 1024)
#define HINIC_CMDQ_BUF_MAX_SIZE 2048U
#define MSG_MAX_IN_SIZE (2048 * 1024)
#define MSG_MAX_OUT_SIZE (2048 * 1024)
static dev_t g_dev_id = {0};
......@@ -50,14 +50,14 @@ static int g_nictool_init_flag;
static int g_nictool_ref_cnt;
typedef int (*nic_driv_module)(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size);
u32 in_size, void *buf_out, u32 *out_size);
struct nic_drv_module_handle {
enum driver_cmd_type driv_cmd_name;
nic_driv_module driv_func;
};
typedef int (*hw_driv_module)(void *hwdev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size);
u32 in_size, void *buf_out, u32 *out_size);
struct hw_drv_module_handle {
enum driver_cmd_type driv_cmd_name;
hw_driv_module driv_func;
......@@ -654,7 +654,7 @@ static int set_link_mode(struct hinic_nic_dev *nic_dev, void *buf_in,
}
static int set_dcb_cfg(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
u32 in_size, void *buf_out, u32 *out_size)
{
union _dcb_ctl dcb_ctl = {.data = 0};
int err;
......@@ -666,8 +666,8 @@ static int set_dcb_cfg(struct hinic_nic_dev *nic_dev, void *buf_in,
dcb_ctl.data = *((u32 *)buf_in);
err = hinic_setup_dcb_tool(nic_dev->netdev,
&dcb_ctl.dcb_data.dcb_en,
!!dcb_ctl.dcb_data.wr_flag);
&dcb_ctl.dcb_data.dcb_en,
!!dcb_ctl.dcb_data.wr_flag);
if (err) {
nicif_err(nic_dev, drv, nic_dev->netdev,
"Failed to setup dcb state to %d\n",
......@@ -682,7 +682,7 @@ static int set_dcb_cfg(struct hinic_nic_dev *nic_dev, void *buf_in,
}
int get_pfc_info(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
u32 in_size, void *buf_out, u32 *out_size)
{
union _pfc pfc = {.data = 0};
......@@ -705,7 +705,7 @@ int get_pfc_info(struct hinic_nic_dev *nic_dev, void *buf_in,
}
int set_pfc_control(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
u32 in_size, void *buf_out, u32 *out_size)
{
u8 pfc_en = 0;
u8 err = 0;
......@@ -737,7 +737,7 @@ int set_pfc_control(struct hinic_nic_dev *nic_dev, void *buf_in,
}
int set_ets(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
u32 in_size, void *buf_out, u32 *out_size)
{
struct _ets ets = {0};
u8 err = 0;
......@@ -801,7 +801,7 @@ int set_ets(struct hinic_nic_dev *nic_dev, void *buf_in,
}
int get_support_up(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
u32 in_size, void *buf_out, u32 *out_size)
{
u8 *up_num = buf_out;
u8 support_up = 0;
......@@ -829,7 +829,7 @@ int get_support_up(struct hinic_nic_dev *nic_dev, void *buf_in,
}
int get_support_tc(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
u32 in_size, void *buf_out, u32 *out_size)
{
u8 *tc_num = buf_out;
......@@ -849,7 +849,7 @@ int get_support_tc(struct hinic_nic_dev *nic_dev, void *buf_in,
}
int get_ets_info(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
u32 in_size, void *buf_out, u32 *out_size)
{
struct _ets *ets = buf_out;
......@@ -868,7 +868,7 @@ int get_ets_info(struct hinic_nic_dev *nic_dev, void *buf_in,
}
int set_pfc_priority(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
u32 in_size, void *buf_out, u32 *out_size)
{
u8 pfc_prority = 0;
u8 err = 0;
......@@ -997,6 +997,7 @@ static int get_homologue(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
{
struct hinic_homologues *homo = buf_out;
if (!buf_out || *out_size != sizeof(*homo)) {
nicif_err(nic_dev, drv, nic_dev->netdev,
"Unexpect out buf size from user: %d, expect: %lu\n",
......@@ -1018,6 +1019,7 @@ static int set_homologue(struct hinic_nic_dev *nic_dev, void *buf_in,
u32 in_size, void *buf_out, u32 *out_size)
{
struct hinic_homologues *homo = buf_in;
if (!buf_in || in_size != sizeof(*homo)) {
nicif_err(nic_dev, drv, nic_dev->netdev,
"Unexpect in buf size from user: %d, expect: %lu\n",
......@@ -1228,6 +1230,7 @@ static int get_device_id(void *hwdev, void *buf_in, u32 in_size,
{
u16 dev_id;
int err;
if (!buf_out || !buf_in || *out_size != sizeof(u16) ||
in_size != sizeof(u16)) {
pr_err("Unexpect out buf size from user: %d, expect: %lu\n",
......@@ -1263,7 +1266,7 @@ static int is_driver_in_vm(void *hwdev, void *buf_in, u32 in_size,
}
static int get_pf_id(void *hwdev, void *buf_in, u32 in_size,
void *buf_out, u32 *out_size)
void *buf_out, u32 *out_size)
{
struct hinic_pf_info *pf_info;
u32 port_id = 0;
......@@ -1898,7 +1901,7 @@ static int send_to_sm(void *hwdev, struct msg_module *nt_msg,
}
static bool is_hwdev_cmd_support(unsigned int mod,
char *ifname, u32 up_api_type)
char *ifname, u32 up_api_type)
{
void *hwdev;
......@@ -1954,7 +1957,7 @@ static bool is_hwdev_cmd_support(unsigned int mod,
}
static bool nictool_k_is_cmd_support(unsigned int mod,
char *ifname, u32 up_api_type)
char *ifname, u32 up_api_type)
{
enum hinic_init_state init_state =
hinic_get_init_state_by_ifname(ifname);
......@@ -1971,7 +1974,7 @@ static bool nictool_k_is_cmd_support(unsigned int mod,
} else if (mod >= SEND_TO_UCODE && mod <= SEND_TO_SM) {
return is_hwdev_cmd_support(mod, ifname, up_api_type);
} else if ((mod >= HINICADM_OVS_DRIVER &&
mod <= HINICADM_FCOE_DRIVER) ||
mod <= HINICADM_FCOE_DRIVER) ||
mod == SEND_TO_HW_DRIVER) {
if (init_state < HINIC_INIT_STATE_HWDEV_INITED) {
pr_err("Hwdev have not initialized\n");
......
drivers/net/ethernet/huawei/hinic/hinic_nictool.h
浏览文件 @ e6a07712
......@@ -50,11 +50,11 @@ struct ipsurx_stats_info {
struct ucode_cmd_st {
union {
struct {
u32 comm_mod_type:8;
u32 ucode_cmd_type:4;
u32 cmdq_ack_type:3;
u32 ucode_imm:1;
u32 len:16;
u32 comm_mod_type : 8;
u32 ucode_cmd_type : 4;
u32 cmdq_ack_type : 3;
u32 ucode_imm : 1;
u32 len : 16;
} ucode_db;
u32 value;
};
......@@ -63,9 +63,9 @@ struct ucode_cmd_st {
struct up_cmd_st {
union {
struct {
u32 comm_mod_type:8;
u32 chipif_cmd:8;
u32 up_api_type:16;
u32 comm_mod_type : 8;
u32 chipif_cmd : 8;
u32 up_api_type : 16;
} up_db;
u32 value;
};
......@@ -97,11 +97,11 @@ union _pfc {
union _flag_com {
struct _ets_flag {
u8 flag_ets_enable:1;
u8 flag_ets_percent:1;
u8 flag_ets_cos:1;
u8 flag_ets_strict:1;
u8 rev:4;
u8 flag_ets_enable : 1;
u8 flag_ets_percent : 1;
u8 flag_ets_cos : 1;
u8 flag_ets_strict : 1;
u8 rev : 4;
} ets_flag;
u8 data;
};
......@@ -166,8 +166,8 @@ struct hinic_tx_hw_page {
struct hinic_dbg_sq_info {
u16 q_id;
u16 pi;
u16 ci;/* sw_ci */
u16 fi;/* hw_ci */
u16 ci; /* sw_ci */
u16 fi; /* hw_ci */
u32 q_depth;
u16 pi_reverse;
......@@ -268,9 +268,9 @@ struct hinic_pf_info {
int nictool_k_init(void);
void nictool_k_uninit(void);
extern u32 hinic_get_io_stats_size(struct hinic_nic_dev *nic_dev);
extern void hinic_get_io_stats(struct hinic_nic_dev *nic_dev,
struct hinic_show_item *items);
u32 hinic_get_io_stats_size(struct hinic_nic_dev *nic_dev);
void hinic_get_io_stats(struct hinic_nic_dev *nic_dev,
struct hinic_show_item *items);
#define TOOL_COUNTER_MAX_LEN 512
......
drivers/net/ethernet/huawei/hinic/hinic_port_cmd.h
浏览文件 @ e6a07712
......@@ -278,7 +278,7 @@ enum hinic_mgmt_cmd {
HINIC_MGMT_CMD_GET_HW_PF_INFOS = 0x6D,
HINIC_MGMT_CMD_GET_SDI_MODE = 0x6E,
HINIC_MGMT_CMD_ENABLE_MIGRATE = 0x6F,
HINIC_MGMT_CMD_ENABLE_MIGRATE = 0x6F,
};
/* uCode relates commands */
......@@ -343,8 +343,8 @@ enum sq_tunnel_l4_type {
TUNNEL_UDP_CSUM,
};
#define NIC_RSS_CMD_TEMP_ALLOC 0x01
#define NIC_RSS_CMD_TEMP_FREE 0x02
#define NIC_RSS_CMD_TEMP_ALLOC 0x01
#define NIC_RSS_CMD_TEMP_FREE 0x02
#define HINIC_RSS_TYPE_VALID_SHIFT 23
#define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24
......@@ -495,7 +495,7 @@ enum {
#define DB_IDX(db, db_base) \
((u32)(((ulong)(db) - (ulong)(db_base)) / \
HINIC_DB_PAGE_SIZE))
HINIC_DB_PAGE_SIZE))
enum hinic_pcie_nosnoop {
HINIC_PCIE_SNOOP = 0,
......@@ -518,21 +518,21 @@ enum hinic_doorbell_ctrl {
};
enum hinic_pf_status {
HINIC_PF_STATUS_INIT = 0X0,
HINIC_PF_STATUS_INIT = 0x0,
HINIC_PF_STATUS_ACTIVE_FLAG = 0x11,
HINIC_PF_STATUS_FLR_START_FLAG = 0x12,
HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,
};
/* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */
#define HINIC_DB_DWQE_SIZE 0x00080000
#define HINIC_DB_DWQE_SIZE 0x00080000
/* BMGW & VMGW VF db size 256k, have no dwqe space */
#define HINIC_GW_VF_DB_SIZE 0x00040000
#define HINIC_GW_VF_DB_SIZE 0x00040000
/* db/dwqe page size: 4K */
#define HINIC_DB_PAGE_SIZE 0x00001000ULL
#define HINIC_DB_PAGE_SIZE 0x00001000ULL
#define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
#define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
#define HINIC_PCI_MSIX_ENTRY_SIZE 16
#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12
......
drivers/net/ethernet/huawei/hinic/hinic_qe_def.h
浏览文件 @ e6a07712
......@@ -16,22 +16,22 @@
#ifndef __HINIC_QE_DEF_H__
#define __HINIC_QE_DEF_H__
#define HINIC_SQ_WQEBB_SIZE 64
#define HINIC_RQ_WQE_SIZE 32
#define HINIC_SQ_WQEBB_SHIFT 6
#define HINIC_RQ_WQEBB_SHIFT 5
#define HINIC_SQ_WQEBB_SIZE 64
#define HINIC_RQ_WQE_SIZE 32
#define HINIC_SQ_WQEBB_SHIFT 6
#define HINIC_RQ_WQEBB_SHIFT 5
#define HINIC_MAX_QUEUE_DEPTH 4096
#define HINIC_MIN_QUEUE_DEPTH 128
#define HINIC_TXD_ALIGN 1
#define HINIC_RXD_ALIGN 1
#define HINIC_TXD_ALIGN 1
#define HINIC_RXD_ALIGN 1
#define HINIC_SQ_DEPTH 1024
#define HINIC_RQ_DEPTH 1024
#define HINIC_RQ_WQE_MAX_SIZE 32
#define HINIC_RQ_WQE_MAX_SIZE 32
#define SIZE_8BYTES(size) (ALIGN((u32)(size), 8) >> 3)//lint !e767
#define SIZE_8BYTES(size) (ALIGN((u32)(size), 8) >> 3)//lint !e767
/************** SQ_CTRL ***************/
#define SQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
......@@ -47,11 +47,11 @@
#define SQ_CTRL_OWNER_MASK 0x1U
#define SQ_CTRL_GET(val, member) (((val) >> SQ_CTRL_##member##_SHIFT) \
& SQ_CTRL_##member##_MASK)
& SQ_CTRL_##member##_MASK)
#define SQ_CTRL_CLEAR(val, member) ((val) & \
(~(SQ_CTRL_##member##_MASK << \
SQ_CTRL_##member##_SHIFT)))
(~(SQ_CTRL_##member##_MASK << \
SQ_CTRL_##member##_SHIFT)))
#define SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT 2
#define SQ_CTRL_QUEUE_INFO_UFO_SHIFT 10
......@@ -73,15 +73,15 @@
#define SQ_CTRL_QUEUE_INFO_SET(val, member) \
(((u32)(val) & SQ_CTRL_QUEUE_INFO_##member##_MASK) \
<< SQ_CTRL_QUEUE_INFO_##member##_SHIFT)
<< SQ_CTRL_QUEUE_INFO_##member##_SHIFT)
#define SQ_CTRL_QUEUE_INFO_GET(val, member) \
(((val) >> SQ_CTRL_QUEUE_INFO_##member##_SHIFT) \
& SQ_CTRL_QUEUE_INFO_##member##_MASK)
& SQ_CTRL_QUEUE_INFO_##member##_MASK)
#define SQ_CTRL_QUEUE_INFO_CLEAR(val, member) \
((val) & (~(SQ_CTRL_QUEUE_INFO_##member##_MASK << \
SQ_CTRL_QUEUE_INFO_##member##_SHIFT)))
SQ_CTRL_QUEUE_INFO_##member##_SHIFT)))
#define SQ_TASK_INFO0_L2HDR_LEN_SHIFT 0
#define SQ_TASK_INFO0_L4OFFLOAD_SHIFT 8
......@@ -103,10 +103,10 @@
#define SQ_TASK_INFO0_SET(val, member) \
(((u32)(val) & SQ_TASK_INFO0_##member##_MASK) << \
SQ_TASK_INFO0_##member##_SHIFT)
SQ_TASK_INFO0_##member##_SHIFT)
#define SQ_TASK_INFO0_GET(val, member) \
(((val) >> SQ_TASK_INFO0_##member##_SHIFT) & \
SQ_TASK_INFO0_##member##_MASK)
SQ_TASK_INFO0_##member##_MASK)
#define SQ_TASK_INFO1_MD_TYPE_SHIFT 8
#define SQ_TASK_INFO1_INNER_L4LEN_SHIFT 16
......@@ -118,10 +118,10 @@
#define SQ_TASK_INFO1_SET(val, member) \
(((val) & SQ_TASK_INFO1_##member##_MASK) << \
SQ_TASK_INFO1_##member##_SHIFT)
SQ_TASK_INFO1_##member##_SHIFT)
#define SQ_TASK_INFO1_GET(val, member) \
(((val) >> SQ_TASK_INFO1_##member##_SHIFT) & \
SQ_TASK_INFO1_##member##_MASK)
SQ_TASK_INFO1_##member##_MASK)
#define SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT 0
#define SQ_TASK_INFO2_OUTER_L3LEN_SHIFT 8
......@@ -135,43 +135,43 @@
#define SQ_TASK_INFO2_SET(val, member) \
(((val) & SQ_TASK_INFO2_##member##_MASK) << \
SQ_TASK_INFO2_##member##_SHIFT)
SQ_TASK_INFO2_##member##_SHIFT)
#define SQ_TASK_INFO2_GET(val, member) \
(((val) >> SQ_TASK_INFO2_##member##_SHIFT) & \
SQ_TASK_INFO2_##member##_MASK)
SQ_TASK_INFO2_##member##_MASK)
#define SQ_TASK_INFO4_L2TYPE_SHIFT 31
#define SQ_TASK_INFO4_L2TYPE_SHIFT 31
#define SQ_TASK_INFO4_L2TYPE_MASK 0x1U
#define SQ_TASK_INFO4_L2TYPE_MASK 0x1U
#define SQ_TASK_INFO4_SET(val, member) \
(((u32)(val) & SQ_TASK_INFO4_##member##_MASK) << \
SQ_TASK_INFO4_##member##_SHIFT)
/********************* SQ_DB *********************/
#define SQ_DB_OFF 0x00000800
#define SQ_DB_INFO_HI_PI_SHIFT 0
#define SQ_DB_INFO_QID_SHIFT 8
#define SQ_DB_INFO_CFLAG_SHIFT 23
#define SQ_DB_INFO_COS_SHIFT 24
#define SQ_DB_INFO_TYPE_SHIFT 27
#define SQ_DB_INFO_HI_PI_MASK 0xFFU
#define SQ_DB_INFO_QID_MASK 0x3FFU
#define SQ_DB_INFO_CFLAG_MASK 0x1U
#define SQ_DB_INFO_COS_MASK 0x7U
#define SQ_DB_INFO_TYPE_MASK 0x1FU
#define SQ_DB_INFO_SET(val, member) (((u32)(val) & \
SQ_DB_INFO_##member##_MASK) << \
SQ_DB_INFO_##member##_SHIFT)
#define SQ_DB_PI_LOW_MASK 0xFF
#define SQ_DB_PI_LOW(pi) ((pi) & SQ_DB_PI_LOW_MASK)
#define SQ_DB_PI_HI_SHIFT 8
#define SQ_DB_PI_HIGH(pi) ((pi) >> SQ_DB_PI_HI_SHIFT)
#define SQ_DB_OFF 0x00000800
#define SQ_DB_INFO_HI_PI_SHIFT 0
#define SQ_DB_INFO_QID_SHIFT 8
#define SQ_DB_INFO_CFLAG_SHIFT 23
#define SQ_DB_INFO_COS_SHIFT 24
#define SQ_DB_INFO_TYPE_SHIFT 27
#define SQ_DB_INFO_HI_PI_MASK 0xFFU
#define SQ_DB_INFO_QID_MASK 0x3FFU
#define SQ_DB_INFO_CFLAG_MASK 0x1U
#define SQ_DB_INFO_COS_MASK 0x7U
#define SQ_DB_INFO_TYPE_MASK 0x1FU
#define SQ_DB_INFO_SET(val, member) \
(((u32)(val) & SQ_DB_INFO_##member##_MASK) << \
SQ_DB_INFO_##member##_SHIFT)
#define SQ_DB_PI_LOW_MASK 0xFF
#define SQ_DB_PI_LOW(pi) ((pi) & SQ_DB_PI_LOW_MASK)
#define SQ_DB_PI_HI_SHIFT 8
#define SQ_DB_PI_HIGH(pi) ((pi) >> SQ_DB_PI_HI_SHIFT)
#define SQ_DB_ADDR(sq, pi) ((u64 *)((sq)->db_addr + SQ_DB_OFF) + \
SQ_DB_PI_LOW(pi))
#define SQ_DB 1
#define SQ_CFLAG_DP 0 /* CFLAG_DATA_PATH */
SQ_DB_PI_LOW(pi))
#define SQ_DB 1
#define SQ_CFLAG_DP 0 /* CFLAG_DATA_PATH */
/*********************** RQ_CTRL ******************/
#define RQ_CTRL_BUFDESC_SECT_LEN_SHIFT 0
......@@ -184,17 +184,17 @@
#define RQ_CTRL_COMPLETE_LEN_MASK 0x3U
#define RQ_CTRL_LEN_MASK 0x3U
#define RQ_CTRL_SET(val, member) (((val) & \
RQ_CTRL_##member##_MASK) << \
RQ_CTRL_##member##_SHIFT)
#define RQ_CTRL_SET(val, member) \
(((val) & RQ_CTRL_##member##_MASK) << \
RQ_CTRL_##member##_SHIFT)
#define RQ_CTRL_GET(val, member) (((val) >> \
RQ_CTRL_##member##_SHIFT) & \
RQ_CTRL_##member##_MASK)
#define RQ_CTRL_GET(val, member) \
(((val) >> RQ_CTRL_##member##_SHIFT) & \
RQ_CTRL_##member##_MASK)
#define RQ_CTRL_CLEAR(val, member) ((val) & \
(~(RQ_CTRL_##member##_MASK << \
RQ_CTRL_##member##_SHIFT)))
#define RQ_CTRL_CLEAR(val, member) \
((val) & (~(RQ_CTRL_##member##_MASK << \
RQ_CTRL_##member##_SHIFT)))
#define RQ_CQE_STATUS_CSUM_ERR_SHIFT 0
#define RQ_CQE_STATUS_NUM_LRO_SHIFT 16
......@@ -215,49 +215,49 @@
#define RQ_CQE_STATUS_RXDONE_MASK 0x1U
#define RQ_CQE_STATUS_FLUSH_MASK 0x1U
#define RQ_CQE_STATUS_GET(val, member) (((val) >> \
RQ_CQE_STATUS_##member##_SHIFT) & \
RQ_CQE_STATUS_##member##_MASK)
#define RQ_CQE_STATUS_GET(val, member) \
(((val) >> RQ_CQE_STATUS_##member##_SHIFT) & \
RQ_CQE_STATUS_##member##_MASK)
#define RQ_CQE_STATUS_CLEAR(val, member) ((val) & \
(~(RQ_CQE_STATUS_##member##_MASK << \
RQ_CQE_STATUS_##member##_SHIFT)))
#define RQ_CQE_STATUS_CLEAR(val, member) \
((val) & (~(RQ_CQE_STATUS_##member##_MASK << \
RQ_CQE_STATUS_##member##_SHIFT)))
#define RQ_CQE_SGE_VLAN_SHIFT 0
#define RQ_CQE_SGE_LEN_SHIFT 16
#define RQ_CQE_SGE_VLAN_SHIFT 0
#define RQ_CQE_SGE_LEN_SHIFT 16
#define RQ_CQE_SGE_VLAN_MASK 0xFFFFU
#define RQ_CQE_SGE_LEN_MASK 0xFFFFU
#define RQ_CQE_SGE_VLAN_MASK 0xFFFFU
#define RQ_CQE_SGE_LEN_MASK 0xFFFFU
#define RQ_CQE_SGE_GET(val, member) (((val) >> \
RQ_CQE_SGE_##member##_SHIFT) & \
RQ_CQE_SGE_##member##_MASK)
#define RQ_CQE_SGE_GET(val, member) \
(((val) >> RQ_CQE_SGE_##member##_SHIFT) & \
RQ_CQE_SGE_##member##_MASK)
#define RQ_CQE_PKT_NUM_SHIFT 1
#define RQ_CQE_PKT_FIRST_LEN_SHIFT 19
#define RQ_CQE_PKT_LAST_LEN_SHIFT 6
#define RQ_CQE_SUPER_CQE_EN_SHIFT 0
#define RQ_CQE_PKT_NUM_SHIFT 1
#define RQ_CQE_PKT_FIRST_LEN_SHIFT 19
#define RQ_CQE_PKT_LAST_LEN_SHIFT 6
#define RQ_CQE_SUPER_CQE_EN_SHIFT 0
#define RQ_CQE_PKT_FIRST_LEN_MASK 0x1FFFU
#define RQ_CQE_PKT_LAST_LEN_MASK 0x1FFFU
#define RQ_CQE_PKT_NUM_MASK 0x1FU
#define RQ_CQE_SUPER_CQE_EN_MASK 0x1
#define RQ_CQE_PKT_FIRST_LEN_MASK 0x1FFFU
#define RQ_CQE_PKT_LAST_LEN_MASK 0x1FFFU
#define RQ_CQE_PKT_NUM_MASK 0x1FU
#define RQ_CQE_SUPER_CQE_EN_MASK 0x1
#define RQ_CQE_PKT_NUM_GET(val, member) (((val) >> \
RQ_CQE_PKT_##member##_SHIFT) & \
RQ_CQE_PKT_##member##_MASK)
#define RQ_CQE_PKT_NUM_GET(val, member) \
(((val) >> RQ_CQE_PKT_##member##_SHIFT) & \
RQ_CQE_PKT_##member##_MASK)
#define HINIC_GET_RQ_CQE_PKT_NUM(pkt_info) RQ_CQE_PKT_NUM_GET(pkt_info, NUM)
#define RQ_CQE_SUPER_CQE_EN_GET(val, member) (((val) >> \
RQ_CQE_##member##_SHIFT) & \
RQ_CQE_##member##_MASK)
#define RQ_CQE_SUPER_CQE_EN_GET(val, member) \
(((val) >> RQ_CQE_##member##_SHIFT) & \
RQ_CQE_##member##_MASK)
#define HINIC_GET_SUPER_CQE_EN(pkt_info) \
RQ_CQE_SUPER_CQE_EN_GET(pkt_info, SUPER_CQE_EN)
#define HINIC_GET_SUPER_CQE_EN_BE(pkt_info) ((pkt_info) & 0x1000000U)
#define RQ_CQE_PKT_LEN_GET(val, member) (((val) >> \
RQ_CQE_PKT_##member##_SHIFT) & \
RQ_CQE_PKT_##member##_MASK)
#define RQ_CQE_PKT_LEN_GET(val, member) \
(((val) >> RQ_CQE_PKT_##member##_SHIFT) & \
RQ_CQE_PKT_##member##_MASK)
#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_SHIFT 21
#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK 0x1U
......@@ -271,23 +271,23 @@
#define RQ_CQE_OFFOLAD_TYPE_RSS_TYPE_SHIFT 24
#define RQ_CQE_OFFOLAD_TYPE_RSS_TYPE_MASK 0xFFU
#define RQ_CQE_OFFOLAD_TYPE_GET(val, member) (((val) >> \
RQ_CQE_OFFOLAD_TYPE_##member##_SHIFT) & \
RQ_CQE_OFFOLAD_TYPE_##member##_MASK)
#define RQ_CQE_OFFOLAD_TYPE_GET(val, member) \
(((val) >> RQ_CQE_OFFOLAD_TYPE_##member##_SHIFT) & \
RQ_CQE_OFFOLAD_TYPE_##member##_MASK)
#define RQ_CQE_PKT_TYPES_NON_L2_MASK 0x800U
#define RQ_CQE_PKT_TYPES_L2_MASK 0x7FU
#define RQ_CQE_PKT_TYPES_NON_L2_MASK 0x800U
#define RQ_CQE_PKT_TYPES_L2_MASK 0x7FU
#define RQ_CQE_STATUS_CSUM_BYPASS_VAL 0x80
#define RQ_CQE_STATUS_CSUM_ERR_IP_MASK 0x31U
#define RQ_CQE_STATUS_CSUM_ERR_L4_MASK 0x4EU
#define RQ_CQE_STATUS_CSUM_BYPASS_VAL 0x80
#define RQ_CQE_STATUS_CSUM_ERR_IP_MASK 0x31U
#define RQ_CQE_STATUS_CSUM_ERR_L4_MASK 0x4EU
#define SECT_SIZE_BYTES(size) ((size) << 3)
#define SECT_SIZE_BYTES(size) ((size) << 3)
#define HINIC_PF_SET_VF_ALREADY 0x4
#define HINIC_MGMT_STATUS_EXIST 0x6
#define HINIC_PF_SET_VF_ALREADY 0x4
#define HINIC_MGMT_STATUS_EXIST 0x6
#define WQS_BLOCKS_PER_PAGE 4
#define WQS_BLOCKS_PER_PAGE 4
#define WQ_SIZE(wq) (u32)((u64)(wq)->q_depth * (wq)->wqebb_size)
......@@ -298,7 +298,7 @@
((idx) & ((wq)->num_wqebbs_per_page - 1)))
#define WQ_PAGE_ADDR_SIZE sizeof(u64)
#define WQ_PAGE_ADDR_SIZE_SHIFT 3
#define WQ_PAGE_ADDR_SIZE_SHIFT 3
#define WQ_PAGE_ADDR(wq, idx) \
(u8 *)(*(u64 *)((u64)((wq)->shadow_block_vaddr) + \
(WQE_PAGE_NUM(wq, idx) << WQ_PAGE_ADDR_SIZE_SHIFT)))
......@@ -310,7 +310,7 @@
#define CMDQ_BLOCKS_PER_PAGE 8
#define CMDQ_BLOCK_SIZE 512UL
#define CMDQ_PAGE_SIZE ALIGN((CMDQ_BLOCKS_PER_PAGE * \
CMDQ_BLOCK_SIZE), PAGE_SIZE)
CMDQ_BLOCK_SIZE), PAGE_SIZE)
#define ADDR_4K_ALIGNED(addr) (0 == ((addr) & 0xfff))
#define ADDR_256K_ALIGNED(addr) (0 == ((addr) & 0x3ffff))
......@@ -342,11 +342,11 @@
#define WQE_SHADOW_PAGE(wq, wqe) \
(u16)(((ulong)(wqe) - (ulong)(wq)->shadow_wqe) \
/ (wq)->max_wqe_size)
/ (wq)->max_wqe_size)
#define WQE_IN_RANGE(wqe, start, end) \
(((ulong)(wqe) >= (ulong)(start)) && \
((ulong)(wqe) < (ulong)(end)))
((ulong)(wqe) < (ulong)(end)))
#define WQ_NUM_PAGES(num_wqs) \
(ALIGN((u32)num_wqs, WQS_BLOCKS_PER_PAGE) / WQS_BLOCKS_PER_PAGE)
......@@ -381,7 +381,7 @@ enum hinic_res_state {
HINIC_RES_ACTIVE = 1,
};
#define DEFAULT_RX_BUF_SIZE ((u16)0xB)
#define DEFAULT_RX_BUF_SIZE ((u16)0xB)
#define BUF_DESC_SIZE_SHIFT 4
......@@ -434,16 +434,16 @@ enum hinic_res_state {
((pkt_types) & RQ_CQE_PKT_TYPES_NON_L2_MASK)
#define HINIC_PKT_TYPES_L2(pkt_types) \
(pkt_types & RQ_CQE_PKT_TYPES_L2_MASK)
((pkt_types) & RQ_CQE_PKT_TYPES_L2_MASK)
#define HINIC_CSUM_ERR_BYPASSED(csum_err) \
(csum_err == RQ_CQE_STATUS_CSUM_BYPASS_VAL)
((csum_err) == RQ_CQE_STATUS_CSUM_BYPASS_VAL)
#define HINIC_CSUM_ERR_IP(csum_err) \
(csum_err & RQ_CQE_STATUS_CSUM_ERR_IP_MASK)
((csum_err) & RQ_CQE_STATUS_CSUM_ERR_IP_MASK)
#define HINIC_CSUM_ERR_L4(csum_err) \
(csum_err & RQ_CQE_STATUS_CSUM_ERR_L4_MASK)
((csum_err) & RQ_CQE_STATUS_CSUM_ERR_L4_MASK)
#define TX_MSS_DEFAULT 0x3E00
#define TX_MSS_MIN 0x50
......
drivers/net/ethernet/huawei/hinic/hinic_rx.c
浏览文件 @ e6a07712
......@@ -48,9 +48,9 @@ static void hinic_clear_rss_config_user(struct hinic_nic_dev *nic_dev);
#define RXQ_STATS_INC(rxq, field) \
{ \
u64_stats_update_begin(&rxq->rxq_stats.syncp); \
rxq->rxq_stats.field++; \
u64_stats_update_end(&rxq->rxq_stats.syncp); \
u64_stats_update_begin(&(rxq)->rxq_stats.syncp); \
(rxq)->rxq_stats.field++; \
u64_stats_update_end(&(rxq)->rxq_stats.syncp); \
}
static bool rx_alloc_mapped_page(struct hinic_rxq *rxq,
......@@ -657,7 +657,7 @@ int hinic_rx_poll(struct hinic_rxq *rxq, int budget)
num_lro = HINIC_GET_RX_NUM_LRO(status);
if (num_lro) {
rx_bytes += ((num_lro - 1) *
LRO_PKT_HDR_LEN(rx_cqe));
LRO_PKT_HDR_LEN(rx_cqe));
num_wqe +=
(u16)(pkt_len >> rxq->rx_buff_shift) +
......
drivers/net/ethernet/huawei/hinic/hinic_rx.h
浏览文件 @ e6a07712
......@@ -30,7 +30,7 @@
#define HINIC_RX_CSUM_OFFLOAD_EN 0xFFF
#define HINIC_SUPPORT_LRO_ADAP_QPS_MAX 16
#define HINIC_RX_BUFFER_WRITE 16
#define HINIC_RX_BUFFER_WRITE 16
struct hinic_rxq_stats {
u64 packets;
......
drivers/net/ethernet/huawei/hinic/hinic_sm_lt.h
浏览文件 @ e6a07712
......@@ -16,27 +16,27 @@
#ifndef __CHIPIF_SM_LT_H__
#define __CHIPIF_SM_LT_H__
#define SM_LT_LOAD (0x12)
#define SM_LT_STORE (0x14)
#define SM_LT_LOAD 0x12
#define SM_LT_STORE 0x14
#define SM_LT_NUM_OFFSET 13
#define SM_LT_ABUF_FLG_OFFSET 12
#define SM_LT_BC_OFFSET 11
#define SM_LT_NUM_OFFSET 13
#define SM_LT_ABUF_FLG_OFFSET 12
#define SM_LT_BC_OFFSET 11
#define SM_LT_ENTRY_16B 16
#define SM_LT_ENTRY_32B 32
#define SM_LT_ENTRY_48B 48
#define SM_LT_ENTRY_64B 64
#define SM_LT_ENTRY_16B 16
#define SM_LT_ENTRY_32B 32
#define SM_LT_ENTRY_48B 48
#define SM_LT_ENTRY_64B 64
#define TBL_LT_OFFSET_DEFAULT 0
#define TBL_LT_OFFSET_DEFAULT 0
#define SM_CACHE_LINE_SHFT 4 /* log2(16) */
#define SM_CACHE_LINE_SIZE 16 /* the size of cache line */
#define SM_CACHE_LINE_SHFT 4 /* log2(16) */
#define SM_CACHE_LINE_SIZE 16 /* the size of cache line */
#define MAX_SM_LT_READ_LINE_NUM 4
#define MAX_SM_LT_WRITE_LINE_NUM 3
#define MAX_SM_LT_READ_LINE_NUM 4
#define MAX_SM_LT_WRITE_LINE_NUM 3
#define SM_LT_FULL_BYTEENB 0xFFFF
#define SM_LT_FULL_BYTEENB 0xFFFF
#define TBL_GET_ENB3_MASK(bitmask) (u16)(((bitmask) >> 32) & 0xFFFF)
#define TBL_GET_ENB2_MASK(bitmask) (u16)(((bitmask) >> 16) & 0xFFFF)
......@@ -52,15 +52,15 @@ enum {
/* lt load request */
typedef union {
struct {
u32 offset:8;
u32 pad:3;
u32 bc:1;
u32 abuf_flg:1;
u32 num:2;
u32 ack:1;
u32 op_id:5;
u32 instance:6;
u32 src:5;
u32 offset : 8;
u32 pad : 3;
u32 bc : 1;
u32 abuf_flg : 1;
u32 num : 2;
u32 ack : 1;
u32 op_id : 5;
u32 instance : 6;
u32 src : 5;
} bs;
u32 value;
......@@ -178,30 +178,30 @@ struct hinic_csr_request_api_data {
union {
struct {
u32 reserved1:13;
u32 reserved1 : 13;
/* this field indicates the write/read data size:
* 2'b00: 32 bits
* 2'b01: 64 bits
* 2'b10~2'b11:reserved
*/
u32 data_size:2;
u32 data_size : 2;
/* this field indicates that requestor expect receive a
* response data or not.
* 1'b0: expect not to receive a response data.
* 1'b1: expect to receive a response data.
*/
u32 need_response:1;
u32 need_response : 1;
/* this field indicates the operation that the requestor
* expected.
* 5'b1_1110: write value to csr space.
* 5'b1_1111: read register from csr space.
*/
u32 operation_id:5;
u32 reserved2:6;
u32 operation_id : 5;
u32 reserved2 : 6;
/* this field specifies the Src node ID for this API
* request message.
*/
u32 src_node_id:5;
u32 src_node_id : 5;
} bits;
u32 val32;
......@@ -210,8 +210,8 @@ struct hinic_csr_request_api_data {
union {
struct {
/* it specifies the CSR address. */
u32 csr_addr:26;
u32 reserved3:6;
u32 csr_addr : 26;
u32 reserved3 : 6;
} bits;
u32 val32;
......
drivers/net/ethernet/huawei/hinic/hinic_sml_counter.h
浏览文件 @ e6a07712
......@@ -16,27 +16,27 @@
#ifndef __CHIPIF_SML_COUNTER_H__
#define __CHIPIF_SML_COUNTER_H__
#define CHIPIF_FUNC_PF 0
#define CHIPIF_FUNC_VF 1
#define CHIPIF_FUNC_PPF 2
#define CHIPIF_FUNC_PF 0
#define CHIPIF_FUNC_VF 1
#define CHIPIF_FUNC_PPF 2
#define CHIPIF_ACK 1
#define CHIPIF_NOACK 0
#define CHIPIF_ACK 1
#define CHIPIF_NOACK 0
#define CHIPIF_SM_CTR_OP_READ 0x2
#define CHIPIF_SM_CTR_OP_READ_CLEAR 0x6
#define CHIPIF_SM_CTR_OP_WRITE 0x3
#define CHIPIF_SM_CTR_OP_READ 0x2
#define CHIPIF_SM_CTR_OP_READ_CLEAR 0x6
#define CHIPIF_SM_CTR_OP_WRITE 0x3
#define SMALL_CNT_READ_RSP_SIZE 16
#define SMALL_CNT_READ_RSP_SIZE 16
/* request head */
typedef union {
struct {
u32 pad:15;
u32 ack:1;
u32 op_id:5;
u32 instance:6;
u32 src:5;
u32 pad : 15;
u32 ack : 1;
u32 op_id : 5;
u32 instance : 6;
u32 src : 5;
} bs;
u32 value;
......@@ -53,8 +53,8 @@ typedef struct {
/* counter read response union */
typedef union {
struct {
u32 value1:16;
u32 pad0:16;
u32 value1 : 16;
u32 pad0 : 16;
u32 pad1[3];
} bs_ss16_rsp;
......@@ -64,10 +64,10 @@ typedef union {
} bs_ss32_rsp;
struct {
u32 value1:20;
u32 pad0:12;
u32 value2:12;
u32 pad1:20;
u32 value1 : 20;
u32 pad0 : 12;
u32 value2 : 12;
u32 pad1 : 20;
u32 pad2[2];
} bs_sp_rsp;
......@@ -89,8 +89,8 @@ typedef union {
/* resopnse head */
typedef union {
struct {
u32 pad:30; /* reserve */
u32 code:2; /* error code */
u32 pad : 30; /* reserve */
u32 code : 2; /* error code */
} bs;
u32 value;
......
drivers/net/ethernet/huawei/hinic/hinic_sml_lt.c
浏览文件 @ e6a07712
......@@ -31,11 +31,11 @@
#include "hinic_hwif.h"
#include "hinic_dbg.h"
#define ACK 1
#define NOACK 0
#define ACK 1
#define NOACK 0
#define LT_LOAD16_API_SIZE (16 + 4)
#define LT_STORE16_API_SIZE (32 + 4)
#define LT_LOAD16_API_SIZE (16 + 4)
#define LT_STORE16_API_SIZE (32 + 4)
#define HINIC_API_RD_8B 8
#define HINIC_API_RD_4B 4
......
drivers/net/ethernet/huawei/hinic/hinic_sriov.c
浏览文件 @ e6a07712
......@@ -280,7 +280,7 @@ int hinic_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting)
return 0;
err = hinic_set_vf_spoofchk(sriov_info->hwdev,
OS_VF_ID_TO_HW(vf), setting);
OS_VF_ID_TO_HW(vf), setting);
if (!err) {
nicif_info(adapter, drv, netdev, "Set VF %d spoofchk %s\n",
......
drivers/net/ethernet/huawei/hinic/hinic_tx.c
浏览文件 @ e6a07712
......@@ -41,16 +41,16 @@
#include "hinic_tx.h"
#include "hinic_dbg.h"
#define MIN_SKB_LEN 32
#define MAX_PAYLOAD_OFFSET 221
#define MIN_SKB_LEN 32
#define MAX_PAYLOAD_OFFSET 221
#define NIC_QID(q_id, nic_dev) ((q_id) & ((nic_dev)->num_qps - 1))
#define TXQ_STATS_INC(txq, field) \
{ \
u64_stats_update_begin(&txq->txq_stats.syncp); \
txq->txq_stats.field++; \
u64_stats_update_end(&txq->txq_stats.syncp); \
u64_stats_update_begin(&(txq)->txq_stats.syncp); \
(txq)->txq_stats.field++; \
u64_stats_update_end(&(txq)->txq_stats.syncp); \
}
void hinic_txq_get_stats(struct hinic_txq *txq,
......@@ -164,7 +164,7 @@ static int tx_map_skb(struct hinic_nic_dev *nic_dev, struct sk_buff *skb,
}
dma_len[0].dma = dma_map_single(&pdev->dev, skb->data,
skb_headlen(skb), DMA_TO_DEVICE);
skb_headlen(skb), DMA_TO_DEVICE);
if (dma_mapping_error(&pdev->dev, dma_len[0].dma)) {
TXQ_STATS_INC(txq, map_frag_err);
err = -EFAULT;
......@@ -184,7 +184,7 @@ static int tx_map_skb(struct hinic_nic_dev *nic_dev, struct sk_buff *skb,
nsize = skb_frag_size(frag);
i++;
dma_len[i].dma = skb_frag_dma_map(&pdev->dev, frag, 0,
nsize, DMA_TO_DEVICE);
nsize, DMA_TO_DEVICE);
if (dma_mapping_error(&pdev->dev, dma_len[i].dma)) {
TXQ_STATS_INC(txq, map_frag_err);
i--;
......@@ -287,6 +287,7 @@ static void get_inner_l3_l4_type(struct sk_buff *skb, union hinic_ip *ip,
*l4_proto = ip->v6->nexthdr;
if (exthdr != l4->hdr) {
__be16 frag_off = 0;
ipv6_skip_exthdr(skb, (int)(exthdr - skb->data),
l4_proto, &frag_off);
}
......
drivers/net/ethernet/huawei/hinic/hinic_wq.c
浏览文件 @ e6a07712
......@@ -34,7 +34,7 @@
#define WQS_MAX_NUM_BLOCKS 256
#define WQS_FREE_BLOCKS_SIZE(wqs) (WQS_MAX_NUM_BLOCKS * \
sizeof((wqs)->free_blocks[0]))
sizeof((wqs)->free_blocks[0]))
static int wqs_next_block(struct hinic_wqs *wqs, u32 *page_idx,
u32 *block_idx);
......@@ -381,8 +381,8 @@ void hinic_wq_wqe_pg_clear(struct hinic_wq *wq)
int hinic_cmdq_alloc(struct hinic_cmdq_pages *cmdq_pages,
struct hinic_wq *wq, void *dev_hdl,
int cmdq_blocks, u32 wq_page_size, u32 wqebb_size,
u16 q_depth, u32 max_wqe_size)
int cmdq_blocks, u32 wq_page_size, u32 wqebb_size,
u16 q_depth, u32 max_wqe_size)
{
int i, j, err = -ENOMEM;
......
drivers/net/ethernet/huawei/hinic/hinic_wq.h
浏览文件 @ e6a07712
......@@ -69,7 +69,7 @@ struct hinic_wqs {
u64 **page_vaddr;
u64 **shadow_page_vaddr;
struct hinic_free_block *free_blocks;
struct hinic_free_block *free_blocks;
u32 alloc_blk_pos;
u32 return_blk_pos;
int num_free_blks;
......@@ -86,8 +86,8 @@ void hinic_wq_wqe_pg_clear(struct hinic_wq *wq);
int hinic_cmdq_alloc(struct hinic_cmdq_pages *cmdq_pages,
struct hinic_wq *wq, void *dev_hdl,
int cmdq_blocks, u32 wq_page_size, u32 wqebb_size,
u16 q_depth, u32 max_wqe_size);
int cmdq_blocks, u32 wq_page_size, u32 wqebb_size,
u16 q_depth, u32 max_wqe_size);
void hinic_cmdq_free(struct hinic_cmdq_pages *cmdq_pages,
struct hinic_wq *wq, int cmdq_blocks);
......@@ -98,7 +98,7 @@ void hinic_wqs_free(struct hinic_wqs *wqs);
int hinic_wq_allocate(struct hinic_wqs *wqs, struct hinic_wq *wq,
u32 wqebb_size, u32 wq_page_size, u16 q_depth,
u32 max_wqe_size);
u32 max_wqe_size);
void hinic_wq_free(struct hinic_wqs *wqs, struct hinic_wq *wq);
......
drivers/net/ethernet/huawei/hinic/ossl_knl.h
浏览文件 @ e6a07712
......@@ -19,21 +19,21 @@
#include "ossl_knl_linux.h"
#define sdk_err(dev, format, ...) \
dev_err(dev, "[COMM]"format, ##__VA_ARGS__)
dev_err(dev, "[COMM]" format, ##__VA_ARGS__)
#define sdk_warn(dev, format, ...) \
dev_warn(dev, "[COMM]"format, ##__VA_ARGS__)
dev_warn(dev, "[COMM]" format, ##__VA_ARGS__)
#define sdk_notice(dev, format, ...) \
dev_notice(dev, "[COMM]"format, ##__VA_ARGS__)
dev_notice(dev, "[COMM]" format, ##__VA_ARGS__)
#define sdk_info(dev, format, ...) \
dev_info(dev, "[COMM]"format, ##__VA_ARGS__)
dev_info(dev, "[COMM]" format, ##__VA_ARGS__)
#define nic_err(dev, format, ...) \
dev_err(dev, "[NIC]"format, ##__VA_ARGS__)
dev_err(dev, "[NIC]" format, ##__VA_ARGS__)
#define nic_warn(dev, format, ...) \
dev_warn(dev, "[NIC]"format, ##__VA_ARGS__)
dev_warn(dev, "[NIC]" format, ##__VA_ARGS__)
#define nic_notice(dev, format, ...) \
dev_notice(dev, "[NIC]"format, ##__VA_ARGS__)
dev_notice(dev, "[NIC]" format, ##__VA_ARGS__)
#define nic_info(dev, format, ...) \
dev_info(dev, "[NIC]"format, ##__VA_ARGS__)
dev_info(dev, "[NIC]" format, ##__VA_ARGS__)
#endif /* OSSL_KNL_H */
drivers/net/ethernet/huawei/hinic/ossl_knl_linux.h
浏览文件 @ e6a07712
......@@ -59,15 +59,15 @@
int local_atoi(const char *name);
#define nicif_err(priv, type, dev, fmt, args...) \
netif_level(err, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(err, priv, type, dev, "[NIC]" fmt, ##args)
#define nicif_warn(priv, type, dev, fmt, args...) \
netif_level(warn, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(warn, priv, type, dev, "[NIC]" fmt, ##args)
#define nicif_notice(priv, type, dev, fmt, args...) \
netif_level(notice, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(notice, priv, type, dev, "[NIC]" fmt, ##args)
#define nicif_info(priv, type, dev, fmt, args...) \
netif_level(info, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(info, priv, type, dev, "[NIC]" fmt, ##args)
#define nicif_dbg(priv, type, dev, fmt, args...) \
netif_level(dbg, priv, type, dev, "[NIC]"fmt, ##args)
netif_level(dbg, priv, type, dev, "[NIC]" fmt, ##args)
#define tasklet_state(tasklet) ((tasklet)->state)
......
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