drivers/irqchip: add sw64 interrupt controller support

Sunway inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I5GDHC

--------------------------------

Add a driver for the SW64 implementation of the CPU interrupt
controller(INTC). In fact, the INTC is just a software simulated
module to connect global interrupt sources to the local interrupt
controller on each core.

In addition, we rename irq-lpc.c and SW64_CHIP3_LPC config.
Signed-off-by: NZhu Donghong <zhudonghong@wxiat.com>
Signed-off-by: NGu Zitao <guzitao@wxiat.com>

arch/sw_64/Kconfig

@@ -234,6 +234,7 @@ config PLATFORM_XUELANG
 	depends on SW64_CHIP3
 	select SPARSE_IRQ
 	select SYS_HAS_EARLY_PRINTK
+	select SW64_INTC_V2
 	help
 	  Sunway chip3 board chipset
 
@@ -736,15 +737,10 @@ endmenu
 
 menu "Boot options"
 
-config SW64_IRQ_CHIP
-	bool
-
 config USE_OF
 	bool "Flattened Device Tree support"
-	select GENERIC_IRQ_CHIP
-	select IRQ_DOMAIN
-	select SW64_IRQ_CHIP
 	select OF
+	select IRQ_DOMAIN
 	help
 	  Include support for flattened device tree machine descriptions.
 

arch/sw_64/chip/chip3/Makefile

@@ -4,5 +4,4 @@ obj-y	:= chip.o i2c-lib.o
 
 obj-$(CONFIG_PCI)	+= pci-quirks.o
 obj-$(CONFIG_PCI_MSI)	+= msi.o vt_msi.o
-obj-$(CONFIG_SW64_IRQ_CHIP)	+= irq_chip.o
 obj-$(CONFIG_CPUFREQ_DEBUGFS)   += cpufreq_debugfs.o

drivers/irqchip/Kconfig

 # SPDX-License-Identifier: GPL-2.0-only
 menu "IRQ chip support"
 
-config SW64_INTC
-	bool "SW64 Platform-Level Interrupt Controller"
-	depends on ACPI && SW64
-	help
-           This enables support for the INTC chip found in SW systems.
-           The INTC controls devices interrupts and connects them to each
-           core's local interrupt controller.
-
-config SW64_CHIP3_LPC
-	bool "SW64 Chip3 Buildin LPC Interrupt Controller"
-	depends on SW64_CHIP3
-	help
-           This enables support for the LPC interrupt controller bultin in
-	   on chip3 series.
-
 config IRQCHIP
 	def_bool y
 	depends on OF_IRQ
@@ -26,6 +11,24 @@ config ARM_GIC
 	select GENERIC_IRQ_MULTI_HANDLER
 	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 
+config SW64_INTC_V2
+	bool "SW64 Interrupt Controller V2"
+	depends on SW64_CHIP3
+	default y
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN
+	help
+           This enables support for the INTC chip found in SW CHIP3 systems.
+           The INTC controls devices interrupts and connects them to each
+           core's local interrupt controller.
+
+config SW64_LPC_INTC
+	bool "SW64 cpu builtin LPC Interrupt Controller"
+	depends on SW64_INTC_V2
+	help
+	   Say yes here to add support for the SW64 cpu builtin LPC
+	   IRQ controller.
+
 config ARM_GIC_PM
 	bool
 	depends on PM

drivers/irqchip/Makefile

@@ -27,8 +27,8 @@ obj-$(CONFIG_ARCH_SUNXI)		+= irq-sun4i.o
 obj-$(CONFIG_ARCH_SUNXI)		+= irq-sunxi-nmi.o
 obj-$(CONFIG_ARCH_SPEAR3XX)		+= spear-shirq.o
 obj-$(CONFIG_ARM_GIC)			+= irq-gic.o irq-gic-common.o
-obj-$(CONFIG_SW64_INTC)			+= irq-intc-v1.o
-obj-$(CONFIG_SW64_CHIP3_LPC)		+= irq-lpc.o
+obj-$(CONFIG_SW64_INTC_V2)     		+= irq-sw64-intc-v2.o
+obj-$(CONFIG_SW64_LPC_INTC)		+= irq-sw64-lpc-intc.o
 obj-$(CONFIG_ARM_GIC_PM)		+= irq-gic-pm.o
 obj-$(CONFIG_ARCH_REALVIEW)		+= irq-gic-realview.o
 obj-$(CONFIG_ARM_GIC_V2M)		+= irq-gic-v2m.o

drivers/irqchip/irq-intc-v1.c

-// SPDX-License-Identifier: GPL-2.0
-
-#include <linux/acpi_iort.h>
-#include <linux/msi.h>
-#include <linux/acpi.h>
-#include <linux/irqdomain.h>
-#include <linux/interrupt.h>
-#include <linux/cpumask.h>
-#include <linux/io.h>
-#include <linux/percpu.h>
-#include <linux/slab.h>
-#include <linux/irqchip.h>
-#include <asm/sw64io.h>
-static void fake_irq_mask(struct irq_data *data)
-{
-}
-
-static void fake_irq_unmask(struct irq_data *data)
-{
-}
-
-static struct irq_chip onchip_intc = {
-	.name           = "SW fake Intc",
-	.irq_mask       = fake_irq_mask,
-	.irq_unmask     = fake_irq_unmask,
-};
-
-static int sw_intc_domain_map(struct irq_domain *d, unsigned int irq,
-				irq_hw_number_t hw)
-{
-	irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
-	irq_set_status_flags(irq, IRQ_LEVEL);
-	return 0;
-}
-
-static const struct irq_domain_ops intc_irq_domain_ops = {
-	.xlate = irq_domain_xlate_onecell,
-	.map = sw_intc_domain_map,
-};
-
-#ifdef CONFIG_ACPI
-
-static int __init
-intc_parse_madt(union acpi_subtable_headers *header,
-		       const unsigned long end)
-{
-	struct acpi_madt_io_sapic *its_entry;
-	static struct irq_domain *root_domain;
-	int intc_irqs = 8, irq_base = NR_IRQS_LEGACY;
-	irq_hw_number_t hwirq_base = 0;
-	int irq_start = -1;
-
-	its_entry = (struct acpi_madt_io_sapic *)header;
-
-	intc_irqs -= hwirq_base; /* calculate # of irqs to allocate */
-
-	irq_base = irq_alloc_descs(irq_start, 16, intc_irqs,
-			numa_node_id());
-	if (irq_base < 0) {
-		WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
-				irq_start);
-		irq_base = irq_start;
-	}
-
-	root_domain = irq_domain_add_legacy(NULL, intc_irqs, irq_base,
-			hwirq_base, &intc_irq_domain_ops, NULL);
-
-	if (!root_domain)
-		pr_err("Failed to create irqdomain");
-
-	irq_set_default_host(root_domain);
-
-	sw64_io_write(0, MCU_DVC_INT_EN, 0xff);
-
-	return 0;
-}
-
-static int __init acpi_intc_init(void)
-{
-	int count = 0;
-
-	count = acpi_table_parse_madt(ACPI_MADT_TYPE_IO_SAPIC,
-			      intc_parse_madt, 0);
-
-	if (count <= 0) {
-		pr_err("No valid intc entries exist\n");
-		return -EINVAL;
-	}
-	return 0;
-}
-#else
-static int __init acpi_intc_init(void)
-{
-	return 0;
-}
-#endif
-
-static int __init intc_init(void)
-{
-	acpi_intc_init();
-
-	return 0;
-}
-subsys_initcall(intc_init);

arch/sw_64/chip/chip3/irq_chip.c → drivers/irqchip/irq-sw64-intc-v2.c

 // SPDX-License-Identifier: GPL-2.0
 #include <linux/irqdomain.h>
 #include <linux/irqchip.h>
-
-#include <asm/irq_impl.h>
+#include <linux/acpi.h>
+#include <linux/acpi_iort.h>
+#include <linux/of_irq.h>
+#include <asm/sw64io.h>
 
 static void fake_irq_mask(struct irq_data *data)
 {
@@ -32,6 +34,64 @@ static const struct irq_domain_ops sw64_intc_domain_ops = {
 	.map = sw64_intc_domain_map,
 };
 
+static int __init
+intc_parse_madt(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_madt_io_sapic *its_entry;
+	static struct irq_domain *root_domain;
+	int intc_irqs = 8, irq_base = NR_IRQS_LEGACY;
+	irq_hw_number_t hwirq_base = 0;
+	int irq_start = -1;
+
+	its_entry = (struct acpi_madt_io_sapic *)header;
+
+	intc_irqs -= hwirq_base; /* calculate # of irqs to allocate */
+
+	irq_base = irq_alloc_descs(irq_start, 16, intc_irqs,
+			numa_node_id());
+	if (irq_base < 0) {
+		WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
+				irq_start);
+		irq_base = irq_start;
+	}
+
+	root_domain = irq_domain_add_legacy(NULL, intc_irqs, irq_base,
+			hwirq_base, &sw64_intc_domain_ops, NULL);
+
+	if (!root_domain)
+		pr_err("Failed to create irqdomain");
+
+	irq_set_default_host(root_domain);
+
+	sw64_io_write(0, MCU_DVC_INT_EN, 0xff);
+
+	return 0;
+}
+
+static int __init acpi_intc_init(void)
+{
+	int count = 0;
+
+	count = acpi_table_parse_madt(ACPI_MADT_TYPE_IO_SAPIC,
+			      intc_parse_madt, 0);
+
+	if (count <= 0) {
+		pr_err("No valid intc entries exist\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int __init intc_init(void)
+{
+	acpi_intc_init();
+
+	return 0;
+}
+
+subsys_initcall(intc_init);
+
 static struct irq_domain *root_domain;
 
 static int __init