提交 dd8cb189 编写于 作者: N Nikola Cornij 提交者: Alex Deucher

drm/amd/display: Increase watermark latencies for DCN3.1

[why]
The original latencies were causing underflow in some modes

[how]
Replace with the up-to-date watermark values based on new measurments
Reviewed-by: NAhmad Othman <ahmad.othman@amd.com>
Acked-by: NAgustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: NNikola Cornij <nikola.cornij@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
上级 4835ea6c
...@@ -366,32 +366,32 @@ static struct wm_table lpddr5_wm_table = { ...@@ -366,32 +366,32 @@ static struct wm_table lpddr5_wm_table = {
.wm_inst = WM_A, .wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333, .pstate_latency_us = 11.65333,
.sr_exit_time_us = 5.32, .sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 6.38, .sr_enter_plus_exit_time_us = 14.5,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_B, .wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333, .pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.82, .sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 11.196, .sr_enter_plus_exit_time_us = 14.5,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_C, .wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333, .pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.89, .sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 11.24, .sr_enter_plus_exit_time_us = 14.5,
.valid = true, .valid = true,
}, },
{ {
.wm_inst = WM_D, .wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG, .wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333, .pstate_latency_us = 11.65333,
.sr_exit_time_us = 9.748, .sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 11.102, .sr_enter_plus_exit_time_us = 14.5,
.valid = true, .valid = true,
}, },
} }
......
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