diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 49dd310ed588da1c26854baf0096b2649b1ee807..db5feb89d4af33308978cef3ee11eaf08e73ee71 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -68,6 +68,8 @@ #include "dmub/dmub_srv.h" +#include "dce/dmub_hw_lock_mgr.h" + #define CTX \ dc->ctx @@ -2321,9 +2323,22 @@ static void commit_planes_for_stream(struct dc *dc, } if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) - if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) - top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable( - top_pipe_to_program->stream_res.tg); + if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { + if (stream && should_use_dmub_lock(stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_dig = 1; + inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; + + dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, + true, + &hw_locks, + &inst_flags); + } else + top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable( + top_pipe_to_program->stream_res.tg); + } if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) dc->hwss.interdependent_update_lock(dc, context, true); @@ -2493,7 +2508,20 @@ static void commit_planes_for_stream(struct dc *dc, top_pipe_to_program->stream_res.tg->funcs->wait_for_state( top_pipe_to_program->stream_res.tg, CRTC_STATE_VACTIVE); - top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable( + + if (stream && should_use_dmub_lock(stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_dig = 1; + inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst; + + dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, + false, + &hw_locks, + &inst_flags); + } else + top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable( top_pipe_to_program->stream_res.tg); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index f7a0e495f215dda3d8b10189c43c5c5ec5602c12..baad087c4f71831561bc9fca4d77f7363bf19c43 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -12,6 +12,8 @@ #include "dc_link_ddc.h" #include "core_status.h" #include "dpcd_defs.h" +#include "dc_dmub_srv.h" +#include "dce/dmub_hw_lock_mgr.h" #define DC_LOGGER \ link->ctx->logger @@ -4030,9 +4032,23 @@ bool dc_link_dp_set_test_pattern( break; } - if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) - pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( - pipe_ctx->stream_res.tg); + if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { + if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_dig = 1; + inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; + + dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, + true, + &hw_locks, + &inst_flags); + } else + pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( + pipe_ctx->stream_res.tg); + } + pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); /* update MSA to requested color space */ pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc, @@ -4059,9 +4075,24 @@ bool dc_link_dp_set_test_pattern( CRTC_STATE_VBLANK); pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); - if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) - pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable( - pipe_ctx->stream_res.tg); + + if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable) { + if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_dig = 1; + inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; + + dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv, + false, + &hw_locks, + &inst_flags); + } else + pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable( + pipe_ctx->stream_res.tg); + } + /* Set Test Pattern state */ link->test_pattern_enabled = true; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile b/drivers/gpu/drm/amd/display/dc/dce/Makefile index f704a8fd52e81bcbf0875581c33fa2b0db525685..973be8f9fd10761e06ba5f51e73dc37ab35e1d7f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dce/Makefile @@ -29,7 +29,8 @@ DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \ dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \ dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \ -dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o dce_panel_cntl.o +dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o dce_panel_cntl.o \ +dmub_hw_lock_mgr.o AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE)) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c new file mode 100644 index 0000000000000000000000000000000000000000..d399270fd17e05c33792483f37d2d5e3fc5294ce --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -0,0 +1,57 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dmub_hw_lock_mgr.h" +#include "dc_dmub_srv.h" +#include "dc_types.h" +#include "core_types.h" + +void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, + bool lock, + union dmub_hw_lock_flags *hw_locks, + struct dmub_hw_lock_inst_flags *inst_flags) +{ + union dmub_rb_cmd cmd = { 0 }; + + cmd.lock_hw.header.type = DMUB_CMD__HW_LOCK; + cmd.lock_hw.header.sub_type = 0; + cmd.lock_hw.header.payload_bytes = sizeof(struct dmub_cmd_lock_hw_data); + cmd.lock_hw.lock_hw_data.client = HW_LOCK_CLIENT_DRIVER; + cmd.lock_hw.lock_hw_data.lock = lock; + cmd.lock_hw.lock_hw_data.hw_locks.u8All = hw_locks->u8All; + memcpy(&cmd.lock_hw.lock_hw_data.inst_flags, inst_flags, sizeof(struct dmub_hw_lock_inst_flags)); + + if (!lock) + cmd.lock_hw.lock_hw_data.should_release = 1; + + dc_dmub_srv_cmd_queue(dmub_srv, &cmd); + dc_dmub_srv_cmd_execute(dmub_srv); + dc_dmub_srv_wait_idle(dmub_srv); +} + +bool should_use_dmub_lock(struct dc_link *link) +{ + return false; +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h new file mode 100644 index 0000000000000000000000000000000000000000..bc5906347493b4d82bbef8b0450459d77b5c9ad9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h @@ -0,0 +1,39 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DMUB_HW_LOCK_MGR_H_ +#define _DMUB_HW_LOCK_MGR_H_ + +#include "dc_dmub_srv.h" +#include "core_types.h" + +void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, + bool lock, + union dmub_hw_lock_flags *hw_locks, + struct dmub_hw_lock_inst_flags *inst_flags); + +bool should_use_dmub_lock(struct dc_link *link); + +#endif /*_DMUB_HW_LOCK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 8d3a125a0cae23df88167eb9158db0f22f8c7d1d..845e7f823a3d3530d5d3fe6c4453295966b9bc81 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -51,6 +51,7 @@ #include "link_hwss.h" #include "dpcd_defs.h" #include "dsc.h" +#include "dce/dmub_hw_lock_mgr.h" #define DC_LOGGER_INIT(logger) @@ -1763,8 +1764,20 @@ void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) if (lock) delay_cursor_until_vupdate(dc, pipe); - dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc, - pipe->stream_res.opp->inst, lock); + if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_cursor = 1; + inst_flags.opp_inst = pipe->stream_res.opp->inst; + + dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, + lock, + &hw_locks, + &inst_flags); + } else + dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc, + pipe->stream_res.opp->inst, lock); } static bool wait_for_reset_trigger_to_occur( diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index db57cb619a0ce05c1f72a7aa3415c9603ac6e44a..789e33fae016229ae70d56ba5c90d65ca513f21c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -49,6 +49,8 @@ #include "dc_link_dp.h" #include "vm_helper.h" #include "dccg.h" +#include "dc_dmub_srv.h" +#include "dce/dmub_hw_lock_mgr.h" #define DC_LOGGER_INIT(logger) @@ -1194,7 +1196,21 @@ void dcn20_pipe_control_lock( (!flip_immediate && pipe->stream_res.gsl_group > 0)) dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate); - if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { + if (pipe->stream && should_use_dmub_lock(pipe->stream->link)) { + union dmub_hw_lock_flags hw_locks = { 0 }; + struct dmub_hw_lock_inst_flags inst_flags = { 0 }; + + hw_locks.bits.lock_pipe = 1; + inst_flags.otg_inst = pipe->stream_res.tg->inst; + + if (pipe->plane_state != NULL) + hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips; + + dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv, + lock, + &hw_locks, + &inst_flags); + } else if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) { if (lock) pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); else diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 7c03c4798348abeb6fe0710fc9120200f329707a..44f74047050aa959e9e01e1be4fca6eace93b154 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -619,6 +619,7 @@ struct dmub_rb_cmd_abm_init_config { }; union dmub_rb_cmd { + struct dmub_rb_cmd_lock_hw lock_hw; struct dmub_rb_cmd_read_modify_write read_modify_write; struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; struct dmub_rb_cmd_burst_write burst_write;