diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 72d5c198e790bdaa5ca9b38f7399f3beb4e147ea..3efe117721aad002edba89fa9be77e25c4230e4d 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -37,7 +37,7 @@ config DEBUG_STACK_USAGE This option will slow down process creation somewhat. -config CONFIG_SMTC_IDLE_HOOK_DEBUG +config SMTC_IDLE_HOOK_DEBUG bool "Enable additional debug checks before going into CPU idle loop" depends on DEBUG_KERNEL && MIPS_MT_SMTC help diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0fc90ba16ae1594d5ad7b9ba2dba771b954f1e05..b12eeee0e9748f841d85de87dfe2f7a7c3503d69 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -137,13 +137,24 @@ static inline void check_wait(void) case CPU_4KEC: case CPU_4KSC: case CPU_5KC: - case CPU_24K: case CPU_25KF: + case CPU_PR4450: + cpu_wait = r4k_wait; + break; + + case CPU_24K: case CPU_34K: + cpu_wait = r4k_wait; + if (read_c0_config7() & MIPS_CONF7_WII) + cpu_wait = r4k_wait_irqoff; + break; + case CPU_74K: - case CPU_PR4450: cpu_wait = r4k_wait; + if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) + cpu_wait = r4k_wait_irqoff; break; + case CPU_TX49XX: cpu_wait = r4k_wait_irqoff; break; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b1233644fcca66e208282666ff946958ffcca1e3..3ea7863c4519c5d19b80d3466b06f19031e8358a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1372,12 +1372,12 @@ void __init per_cpu_trap_init(void) */ if (cpu_has_mips_r2) { cp0_compare_irq = (read_c0_intctl () >> 29) & 7; - cp0_perfcount_irq = -1; - } else { - cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7; - if (cp0_perfcount_irq != cp0_compare_irq) + if (cp0_perfcount_irq == cp0_compare_irq) cp0_perfcount_irq = -1; + } else { + cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; + cp0_perfcount_irq = -1; } #ifdef CONFIG_MIPS_MT_SMTC diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index c9ee9d2d5856a896a64e16321c92b37a174b7c6d..9e66354dee8b1e15df6568ddd2903609dacc0d7a 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1436,10 +1436,6 @@ static int __init vpe_module_init(void) write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); if (i != 0) { - write_vpe_c0_status((read_c0_status() & - ~(ST0_IM | ST0_IE | ST0_KSU)) - | ST0_CU0); - /* * Set config to be the same as vpe0, * particularly kseg0 coherency alg diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 5dad13efba7edb861607d33a81289f816dbcfa02..1c1aa9f92f6c0ebbbd7781009e03002304c5a364 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -9,4 +9,4 @@ obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o # libgcc-style stuff needed in the kernel -lib-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o +obj-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index c6275088cf65aaa1826e426e9e683b6c3e1f371c..964c5eddc21bf0544a263f748858bbf8ac11a07b 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -133,6 +133,7 @@ || defined (CONFIG_CPU_R4X00) \ || defined (CONFIG_CPU_R5000) \ || defined (CONFIG_CPU_RM7000) \ + || defined (CONFIG_CPU_RM9000) \ || defined (CONFIG_CPU_NEVADA) \ || defined (CONFIG_CPU_TX49XX) \ || defined (CONFIG_CPU_MIPS64) diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index d38fdbf845b2612354a45c4fdfa6273f13aff156..2924069075e0a3b3a3342868d593de128ed880cc 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -124,6 +124,17 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 +/* + * Older processors used to encode processor version and revision in two + * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores + * have switched to use the 8-bits as 3:3:2 bitfield with the last field as + * the patch number. *ARGH* + */ +#define PRID_REV_ENCODE_44(ver, rev) \ + ((ver) << 4 | (rev)) +#define PRID_REV_ENCODE_332(ver, rev, patch) \ + ((ver) << 5 | (rev) << 2 | (patch)) + /* * FPU implementation/revision register (CP1 control register 0). * diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 9985cb7c16e726e22f90ef58f50692920c73ced6..89c81922d47cea5c5ea229cc6c87f1b5e525b9b7 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -534,6 +534,8 @@ #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) +#define MIPS_CONF7_WII (_ULCAST_(1) << 31) + /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 13a3502eef44691e02f44b17b5f19132b933f2bb..ec0eeebd880206a4c71f444c634c54812ffaf3bd 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -177,18 +177,22 @@ #endif /* - * The RM9000 has a bug (though PMC-Sierra opposes it being called that) - * where invalid instructions in the same I-cache line worth of instructions - * being fetched may case spurious exceptions. - */ -#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ - defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) + * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra + * opposes it being called that) where invalid instructions in the same + * I-cache line worth of instructions being fetched may case spurious + * exceptions. + */ +#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \ + defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \ + defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \ + defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \ + defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC) #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif /* - * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that + * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ #ifdef CONFIG_SGI_IP27