From d9d8e6b3c01386e5b39b70dc07156ff0e407d984 Mon Sep 17 00:00:00 2001
From: Sonika Jindal <sonika.jindal@intel.com>
Date: Thu, 11 Dec 2014 17:58:15 +0530
Subject: [PATCH] drm/i915/skl: Correcting the flushing of pipe

We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_pm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f7ceba2032f..8a960d19374b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3004,9 +3004,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
 		    skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
 			skl_wm_flush_pipe(dev_priv, pipe, 2);
 			intel_wait_for_vblank(dev, pipe);
+			reallocated[pipe] = true;
 		}
-
-		reallocated[pipe] = true;
 	}
 
 	/*
-- 
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