From d30cecbcbe149a36a354757cea835c1bb28689cf Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 27 May 2009 17:29:37 +0100 Subject: [PATCH] MIPS: Don't write ones to reserved entryhi bits. We've silently been relying on the hardware chopping off excess, reserved ASID bits for no better reason that it saving an instruction. Because we already have: #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) in . We can use a cleanup to avoid writing non-zero bits into the reserved entryhi bits. This avoid triggering some debugging assertion in the Cavium simulator. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mmu_context.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d9743536a621..ed331c2e4882 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -165,12 +165,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, * having ASID_MASK smaller than the hardware maximum, * make sure no "soft" bits become "hard"... */ - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) - | (cpu_context(cpu, next) & ASID_MASK)); + write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | + cpu_asid(cpu, next)); ehb(); /* Make sure it propagates to TCStatus */ evpe(mtflags); #else - write_c0_entryhi(cpu_context(cpu, next)); + write_c0_entryhi(cpu_asid(cpu, next)); #endif /* CONFIG_MIPS_MT_SMTC */ TLBMISS_HANDLER_SETUP_PGD(next->pgd); @@ -226,11 +226,11 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) } /* See comments for similar code above */ write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | - (cpu_context(cpu, next) & ASID_MASK)); + cpu_asid(cpu, next)); ehb(); /* Make sure it propagates to TCStatus */ evpe(mtflags); #else - write_c0_entryhi(cpu_context(cpu, next)); + write_c0_entryhi(cpu_asid(cpu, next)); #endif /* CONFIG_MIPS_MT_SMTC */ TLBMISS_HANDLER_SETUP_PGD(next->pgd); -- GitLab