diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index 369562d34d66a7ffb7ecbcd0382cd64475a1a1fa..2c1b04497e4be3d48a0bc298b5e16c2227c7bc6a 100644
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -3266,6 +3266,13 @@ static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id)
 	return 0;
 }
 
+static void hisi_qm_set_state(struct hisi_qm *qm, enum vf_state state)
+{
+	/* set vf driver state */
+	if (qm->ver > QM_HW_V2)
+		writel(state, qm->io_base + QM_VF_STATE);
+}
+
 static void hisi_qm_pre_init(struct hisi_qm *qm)
 {
 	struct pci_dev *pdev = qm->pdev;
@@ -3365,6 +3372,8 @@ void hisi_qm_uninit(struct hisi_qm *qm)
 				  qm->qdma.va, qm->qdma.dma);
 	}
 
+	hisi_qm_set_state(qm, VF_NOT_READY);
+
 	qm_irq_unregister(qm);
 	hisi_qm_pci_uninit(qm);
 	uacce_remove(qm->uacce);
@@ -3578,6 +3587,8 @@ int hisi_qm_start(struct hisi_qm *qm)
 	if (!ret)
 		atomic_set(&qm->status.flags, QM_START);
 
+	hisi_qm_set_state(qm, VF_READY);
+
 err_unlock:
 	up_write(&qm->qps_lock);
 	return ret;
@@ -3672,6 +3683,8 @@ int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)
 	struct device *dev = &qm->pdev->dev;
 	int ret = 0;
 
+	hisi_qm_set_state(qm, VF_PREPARE);
+
 	down_write(&qm->qps_lock);
 
 	qm->status.stop_reason = r;
@@ -5640,6 +5653,8 @@ static int hisi_qm_pci_init(struct hisi_qm *qm)
 		goto err_get_pci_res;
 	pci_set_master(pdev);
 
+	hisi_qm_set_state(qm, VF_PREPARE);
+
 	if (!qm->ops->get_irq_num) {
 		ret = -EOPNOTSUPP;
 		goto err_get_pci_res;
diff --git a/drivers/crypto/hisilicon/qm.h b/drivers/crypto/hisilicon/qm.h
index 3068093229a506e749f1c444a441f6b351136a9c..718687dd7242764cc5b5b33cc58f204a7cd74846 100644
--- a/drivers/crypto/hisilicon/qm.h
+++ b/drivers/crypto/hisilicon/qm.h
@@ -80,6 +80,7 @@
 #define QM_SHAPER_CFG			0x100164
 #define QM_SHAPER_ENABLE		BIT(30)
 #define QM_SHAPER_TYPE1_OFFSET		10
+#define QM_VF_STATE			0x0060
 
 /* page number for queue file region */
 #define QM_DOORBELL_PAGE_NR		1
@@ -109,6 +110,12 @@ enum qp_state {
 	QP_CLOSE,
 };
 
+enum vf_state {
+	VF_READY = 0x0,
+	VF_NOT_READY,
+	VF_PREPARE,
+};
+
 enum qm_hw_ver {
 	QM_HW_UNKNOWN = -1,
 	QM_HW_V1 = 0x20,