From c6ea2f5687b5d7f9d9028b9b1e43e3ab836b55d6 Mon Sep 17 00:00:00 2001 From: Zheng Chongzhen Date: Fri, 6 Jan 2023 09:18:07 +0800 Subject: [PATCH] =?UTF-8?q?sw64:=C2=A0iommu:=C2=A0fix=C2=A0the=C2=A0mask?= =?UTF-8?q?=C2=A0of=C2=A0physical=C2=A0address=C2=A0when=C2=A0flushing?= =?UTF-8?q?=C2=A0pcache?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sunway inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I6ILC2 -------------------------------- PCACHE_FLUSHPADDR reg specifies addr[47:7] of the physical address of the pte to be flushed, and other bits reserved, so we can write the physical address directly into the reg. Signed-off-by: Zheng Chongzhen Reviewed-by: He Sheng Signed-off-by: Gu Zitao --- drivers/iommu/sw64/sunway_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/sw64/sunway_iommu.c b/drivers/iommu/sw64/sunway_iommu.c index 580619c6a571..60391678725f 100644 --- a/drivers/iommu/sw64/sunway_iommu.c +++ b/drivers/iommu/sw64/sunway_iommu.c @@ -167,7 +167,7 @@ flush_device_tlb(struct sunway_iommu_domain *sdomain, switch (hflush_addr) { case PCACHE_FLUSHPADDR: - flush_addr = __pa(flush_addr) & 0xffffffff80; + flush_addr = __pa(flush_addr); /* Set memory bar here */ mb(); write_piu_ior0(hose->node, hose->index, -- GitLab