提交 c6e13b52 编写于 作者: M Mark A. Grondona 提交者: Mauro Carvalho Chehab

EDAC: Fix incorrect edac mode reporting in sb_edac

The edac driver for Sandy Bridge was found to be reporting "FPM"
for edac_mode, which clearly doesn't make sense. It was found that
sb_edac.c:get_dimm_config was reusing a variable for both mem_type
and edac_type, and thus was overwriting the value after setting
it correctly. This patch fixes that issue.

Before the patch:
/sys/devices/system/edac/mc/mc0/csrow0/edac_mode:FPM
/sys/devices/system/edac/mc/mc0/csrow1/edac_mode:FPM
/sys/devices/system/edac/mc/mc0/csrow2/edac_mode:FPM
/sys/devices/system/edac/mc/mc0/csrow3/edac_mode:FPM

After:
/sys/devices/system/edac/mc/mc0/csrow0/edac_mode:S4ECD4ED
/sys/devices/system/edac/mc/mc0/csrow1/edac_mode:S4ECD4ED
/sys/devices/system/edac/mc/mc0/csrow2/edac_mode:S4ECD4ED
/sys/devices/system/edac/mc/mc0/csrow3/edac_mode:S4ECD4ED
Signed-off-by: NMark A. Grondona <mgrondona@llnl.gov>
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
上级 3d78c9af
...@@ -559,6 +559,7 @@ static int get_dimm_config(const struct mem_ctl_info *mci) ...@@ -559,6 +559,7 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
unsigned long last_page = 0; unsigned long last_page = 0;
u32 reg; u32 reg;
enum edac_type mode; enum edac_type mode;
enum mem_type mtype;
pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg); pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
pvt->sbridge_dev->source_id = SOURCE_ID(reg); pvt->sbridge_dev->source_id = SOURCE_ID(reg);
...@@ -601,10 +602,10 @@ static int get_dimm_config(const struct mem_ctl_info *mci) ...@@ -601,10 +602,10 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
if (IS_RDIMM_ENABLED(reg)) { if (IS_RDIMM_ENABLED(reg)) {
/* FIXME: Can also be LRDIMM */ /* FIXME: Can also be LRDIMM */
debugf0("Memory is registered\n"); debugf0("Memory is registered\n");
mode = MEM_RDDR3; mtype = MEM_RDDR3;
} else { } else {
debugf0("Memory is unregistered\n"); debugf0("Memory is unregistered\n");
mode = MEM_DDR3; mtype = MEM_DDR3;
} }
/* On all supported DDR3 DIMM types, there are 8 banks available */ /* On all supported DDR3 DIMM types, there are 8 banks available */
...@@ -643,7 +644,7 @@ static int get_dimm_config(const struct mem_ctl_info *mci) ...@@ -643,7 +644,7 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4; csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
csr->ce_count = 0; csr->ce_count = 0;
csr->ue_count = 0; csr->ue_count = 0;
csr->mtype = mode; csr->mtype = mtype;
csr->edac_mode = mode; csr->edac_mode = mode;
csr->nr_channels = 1; csr->nr_channels = 1;
csr->channels[0].chan_idx = i; csr->channels[0].chan_idx = i;
......
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