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提交 c46917bb 编写于 作者: L Luis R. Rodriguez 提交者： John W. Linville
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atheros: add common debug printing 

ath9k uses this for now, ath9k_htc is expected to re-use this
as well. We lave ath5k as is, but it certainly can also be
converted later.

The ath9k module parameter and debugfs entry is kept.
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 cd9bf689
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Showing with 1005 addition and 773 deletion
drivers/net/wireless/ath/Kconfig
浏览文件 @ c46917bb
...@@ -16,7 +16,15 @@ menuconfig ATH_COMMON ...@@ -16,7 +16,15 @@ menuconfig ATH_COMMON
http://wireless.kernel.org/en/users/Drivers/Atheros http://wireless.kernel.org/en/users/Drivers/Atheros
if ATH_COMMON if ATH_COMMON
config ATH_DEBUG
bool "Atheros wireless debugging"
---help---
Say Y, if you want to debug atheros wireless drivers.
Right now only ath9k makes use of this.
source "drivers/net/wireless/ath/ath5k/Kconfig" source "drivers/net/wireless/ath/ath5k/Kconfig"
source "drivers/net/wireless/ath/ath9k/Kconfig" source "drivers/net/wireless/ath/ath9k/Kconfig"
source "drivers/net/wireless/ath/ar9170/Kconfig" source "drivers/net/wireless/ath/ar9170/Kconfig"
endif endif
drivers/net/wireless/ath/Makefile
浏览文件 @ c46917bb
...@@ -7,3 +7,5 @@ obj-$(CONFIG_ATH_COMMON) += ath.o ...@@ -7,3 +7,5 @@ obj-$(CONFIG_ATH_COMMON) += ath.o
ath-objs := main.o \ ath-objs := main.o \
regd.o \ regd.o \
hw.o hw.o
ath-$(CONFIG_ATH_DEBUG) += debug.o
drivers/net/wireless/ath/ath.h
浏览文件 @ c46917bb
...@@ -48,11 +48,14 @@ struct ath_ops { ...@@ -48,11 +48,14 @@ struct ath_ops {
struct ath_common { struct ath_common {
void *ah; void *ah;
struct ieee80211_hw *hw; struct ieee80211_hw *hw;
int debug_mask;
u16 cachelsz; u16 cachelsz;
u16 curaid; u16 curaid;
u8 macaddr[ETH_ALEN]; u8 macaddr[ETH_ALEN];
u8 curbssid[ETH_ALEN]; u8 curbssid[ETH_ALEN];
u8 bssidmask[ETH_ALEN]; u8 bssidmask[ETH_ALEN];
struct ath_regulatory regulatory; struct ath_regulatory regulatory;
const struct ath_ops *ops; const struct ath_ops *ops;
}; };
......
drivers/net/wireless/ath/ath9k/Kconfig
浏览文件 @ c46917bb
...@@ -16,6 +16,8 @@ config ATH9K ...@@ -16,6 +16,8 @@ config ATH9K
If you choose to build a module, it'll be called ath9k. If you choose to build a module, it'll be called ath9k.
if ATH_DEBUG
config ATH9K_DEBUG config ATH9K_DEBUG
bool "Atheros ath9k debugging" bool "Atheros ath9k debugging"
depends on ATH9K depends on ATH9K
...@@ -26,3 +28,5 @@ config ATH9K_DEBUG ...@@ -26,3 +28,5 @@ config ATH9K_DEBUG
modprobe ath9k debug=0x00000200 modprobe ath9k debug=0x00000200
Look in ath9k/debug.h for possible debug masks Look in ath9k/debug.h for possible debug masks
endif # ATH_DEBUG
drivers/net/wireless/ath/ath9k/ahb.c
浏览文件 @ c46917bb
...@@ -40,8 +40,9 @@ static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) ...@@ -40,8 +40,9 @@ static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
pdata = (struct ath9k_platform_data *) pdev->dev.platform_data; pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
"%s: flash read failed, offset %08x is out of range\n", "%s: flash read failed, offset %08x "
"is out of range\n",
__func__, off); __func__, off);
return false; return false;
} }
......
drivers/net/wireless/ath/ath9k/ani.c
浏览文件 @ c46917bb
...@@ -31,7 +31,7 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, ...@@ -31,7 +31,7 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
} }
} }
DPRINTF(ah, ATH_DBG_ANI, ath_print(ath9k_hw_common(ah), ATH_DBG_ANI,
"No more channel states left. Using channel 0\n"); "No more channel states left. Using channel 0\n");
return 0; return 0;
...@@ -41,13 +41,14 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, ...@@ -41,13 +41,14 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
enum ath9k_ani_cmd cmd, int param) enum ath9k_ani_cmd cmd, int param)
{ {
struct ar5416AniState *aniState = ah->curani; struct ar5416AniState *aniState = ah->curani;
struct ath_common *common = ath9k_hw_common(ah);
switch (cmd & ah->ani_function) { switch (cmd & ah->ani_function) {
case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
u32 level = param; u32 level = param;
if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"level out of range (%u > %u)\n", "level out of range (%u > %u)\n",
level, level,
(unsigned)ARRAY_SIZE(ah->totalSizeDesired)); (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
...@@ -152,7 +153,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, ...@@ -152,7 +153,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
u32 level = param; u32 level = param;
if (level >= ARRAY_SIZE(firstep)) { if (level >= ARRAY_SIZE(firstep)) {
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"level out of range (%u > %u)\n", "level out of range (%u > %u)\n",
level, level,
(unsigned) ARRAY_SIZE(firstep)); (unsigned) ARRAY_SIZE(firstep));
...@@ -174,11 +175,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, ...@@ -174,11 +175,10 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
u32 level = param; u32 level = param;
if (level >= ARRAY_SIZE(cycpwrThr1)) { if (level >= ARRAY_SIZE(cycpwrThr1)) {
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"level out of range (%u > %u)\n", "level out of range (%u > %u)\n",
level, level,
(unsigned) (unsigned) ARRAY_SIZE(cycpwrThr1));
ARRAY_SIZE(cycpwrThr1));
return false; return false;
} }
REG_RMW_FIELD(ah, AR_PHY_TIMING5, REG_RMW_FIELD(ah, AR_PHY_TIMING5,
...@@ -194,25 +194,28 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, ...@@ -194,25 +194,28 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
case ATH9K_ANI_PRESENT: case ATH9K_ANI_PRESENT:
break; break;
default: default:
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"invalid cmd %u\n", cmd); "invalid cmd %u\n", cmd);
return false; return false;
} }
DPRINTF(ah, ATH_DBG_ANI, "ANI parameters:\n"); ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"noiseImmunityLevel=%d, spurImmunityLevel=%d, " "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
"ofdmWeakSigDetectOff=%d\n", "ofdmWeakSigDetectOff=%d\n",
aniState->noiseImmunityLevel, aniState->spurImmunityLevel, aniState->noiseImmunityLevel,
aniState->spurImmunityLevel,
!aniState->ofdmWeakSigDetectOff); !aniState->ofdmWeakSigDetectOff);
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"cckWeakSigThreshold=%d, " "cckWeakSigThreshold=%d, "
"firstepLevel=%d, listenTime=%d\n", "firstepLevel=%d, listenTime=%d\n",
aniState->cckWeakSigThreshold, aniState->firstepLevel, aniState->cckWeakSigThreshold,
aniState->firstepLevel,
aniState->listenTime); aniState->listenTime);
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
aniState->cycleCount, aniState->ofdmPhyErrCount, aniState->cycleCount,
aniState->ofdmPhyErrCount,
aniState->cckPhyErrCount); aniState->cckPhyErrCount);
return true; return true;
...@@ -231,6 +234,7 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah, ...@@ -231,6 +234,7 @@ static void ath9k_hw_update_mibstats(struct ath_hw *ah,
static void ath9k_ani_restart(struct ath_hw *ah) static void ath9k_ani_restart(struct ath_hw *ah)
{ {
struct ar5416AniState *aniState; struct ar5416AniState *aniState;
struct ath_common *common = ath9k_hw_common(ah);
if (!DO_ANI(ah)) if (!DO_ANI(ah))
return; return;
...@@ -240,7 +244,7 @@ static void ath9k_ani_restart(struct ath_hw *ah) ...@@ -240,7 +244,7 @@ static void ath9k_ani_restart(struct ath_hw *ah)
if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
aniState->ofdmPhyErrBase = 0; aniState->ofdmPhyErrBase = 0;
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"OFDM Trigger is too high for hw counters\n"); "OFDM Trigger is too high for hw counters\n");
} else { } else {
aniState->ofdmPhyErrBase = aniState->ofdmPhyErrBase =
...@@ -248,13 +252,13 @@ static void ath9k_ani_restart(struct ath_hw *ah) ...@@ -248,13 +252,13 @@ static void ath9k_ani_restart(struct ath_hw *ah)
} }
if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) { if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
aniState->cckPhyErrBase = 0; aniState->cckPhyErrBase = 0;
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"CCK Trigger is too high for hw counters\n"); "CCK Trigger is too high for hw counters\n");
} else { } else {
aniState->cckPhyErrBase = aniState->cckPhyErrBase =
AR_PHY_COUNTMAX - aniState->cckTrigHigh; AR_PHY_COUNTMAX - aniState->cckTrigHigh;
} }
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Writing ofdmbase=%u cckbase=%u\n", "Writing ofdmbase=%u cckbase=%u\n",
aniState->ofdmPhyErrBase, aniState->ofdmPhyErrBase,
aniState->cckPhyErrBase); aniState->cckPhyErrBase);
...@@ -464,6 +468,7 @@ void ath9k_ani_reset(struct ath_hw *ah) ...@@ -464,6 +468,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
{ {
struct ar5416AniState *aniState; struct ar5416AniState *aniState;
struct ath9k_channel *chan = ah->curchan; struct ath9k_channel *chan = ah->curchan;
struct ath_common *common = ath9k_hw_common(ah);
int index; int index;
if (!DO_ANI(ah)) if (!DO_ANI(ah))
...@@ -475,7 +480,7 @@ void ath9k_ani_reset(struct ath_hw *ah) ...@@ -475,7 +480,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
&& ah->opmode != NL80211_IFTYPE_ADHOC) { && ah->opmode != NL80211_IFTYPE_ADHOC) {
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Reset ANI state opmode %u\n", ah->opmode); "Reset ANI state opmode %u\n", ah->opmode);
ah->stats.ast_ani_reset++; ah->stats.ast_ani_reset++;
...@@ -543,6 +548,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, ...@@ -543,6 +548,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
struct ath9k_channel *chan) struct ath9k_channel *chan)
{ {
struct ar5416AniState *aniState; struct ar5416AniState *aniState;
struct ath_common *common = ath9k_hw_common(ah);
int32_t listenTime; int32_t listenTime;
u32 phyCnt1, phyCnt2; u32 phyCnt1, phyCnt2;
u32 ofdmPhyErrCnt, cckPhyErrCnt; u32 ofdmPhyErrCnt, cckPhyErrCnt;
...@@ -569,20 +575,22 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, ...@@ -569,20 +575,22 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
if (phyCnt1 < aniState->ofdmPhyErrBase || if (phyCnt1 < aniState->ofdmPhyErrBase ||
phyCnt2 < aniState->cckPhyErrBase) { phyCnt2 < aniState->cckPhyErrBase) {
if (phyCnt1 < aniState->ofdmPhyErrBase) { if (phyCnt1 < aniState->ofdmPhyErrBase) {
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"phyCnt1 0x%x, resetting " "phyCnt1 0x%x, resetting "
"counter value to 0x%x\n", "counter value to 0x%x\n",
phyCnt1, aniState->ofdmPhyErrBase); phyCnt1,
aniState->ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1, REG_WRITE(ah, AR_PHY_ERR_1,
aniState->ofdmPhyErrBase); aniState->ofdmPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_MASK_1, REG_WRITE(ah, AR_PHY_ERR_MASK_1,
AR_PHY_ERR_OFDM_TIMING); AR_PHY_ERR_OFDM_TIMING);
} }
if (phyCnt2 < aniState->cckPhyErrBase) { if (phyCnt2 < aniState->cckPhyErrBase) {
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"phyCnt2 0x%x, resetting " "phyCnt2 0x%x, resetting "
"counter value to 0x%x\n", "counter value to 0x%x\n",
phyCnt2, aniState->cckPhyErrBase); phyCnt2,
aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_2, REG_WRITE(ah, AR_PHY_ERR_2,
aniState->cckPhyErrBase); aniState->cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_MASK_2, REG_WRITE(ah, AR_PHY_ERR_MASK_2,
...@@ -624,7 +632,9 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, ...@@ -624,7 +632,9 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
void ath9k_enable_mib_counters(struct ath_hw *ah) void ath9k_enable_mib_counters(struct ath_hw *ah)
{ {
DPRINTF(ah, ATH_DBG_ANI, "Enable MIB counters\n"); struct ath_common *common = ath9k_hw_common(ah);
ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
...@@ -640,7 +650,10 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) ...@@ -640,7 +650,10 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
/* Freeze the MIB counters, get the stats and then clear them */ /* Freeze the MIB counters, get the stats and then clear them */
void ath9k_hw_disable_mib_counters(struct ath_hw *ah) void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
{ {
DPRINTF(ah, ATH_DBG_ANI, "Disable MIB counters\n"); struct ath_common *common = ath9k_hw_common(ah);
ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
...@@ -653,6 +666,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, ...@@ -653,6 +666,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
u32 *rxf_pcnt, u32 *rxf_pcnt,
u32 *txf_pcnt) u32 *txf_pcnt)
{ {
struct ath_common *common = ath9k_hw_common(ah);
static u32 cycles, rx_clear, rx_frame, tx_frame; static u32 cycles, rx_clear, rx_frame, tx_frame;
u32 good = 1; u32 good = 1;
...@@ -662,7 +676,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, ...@@ -662,7 +676,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
u32 cc = REG_READ(ah, AR_CCCNT); u32 cc = REG_READ(ah, AR_CCCNT);
if (cycles == 0 || cycles > cc) { if (cycles == 0 || cycles > cc) {
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"cycle counter wrap. ExtBusy = 0\n"); "cycle counter wrap. ExtBusy = 0\n");
good = 0; good = 0;
} else { } else {
...@@ -762,9 +776,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah) ...@@ -762,9 +776,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
void ath9k_hw_ani_init(struct ath_hw *ah) void ath9k_hw_ani_init(struct ath_hw *ah)
{ {
struct ath_common *common = ath9k_hw_common(ah);
int i; int i;
DPRINTF(ah, ATH_DBG_ANI, "Initialize ANI\n"); ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
memset(ah->ani, 0, sizeof(ah->ani)); memset(ah->ani, 0, sizeof(ah->ani));
for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
...@@ -786,10 +801,10 @@ void ath9k_hw_ani_init(struct ath_hw *ah) ...@@ -786,10 +801,10 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
} }
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Setting OfdmErrBase = 0x%08x\n", "Setting OfdmErrBase = 0x%08x\n",
ah->ani[0].ofdmPhyErrBase); ah->ani[0].ofdmPhyErrBase);
DPRINTF(ah, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", ath_print(common, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
ah->ani[0].cckPhyErrBase); ah->ani[0].cckPhyErrBase);
REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
...@@ -803,7 +818,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) ...@@ -803,7 +818,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
void ath9k_hw_ani_disable(struct ath_hw *ah) void ath9k_hw_ani_disable(struct ath_hw *ah)
{ {
DPRINTF(ah, ATH_DBG_ANI, "Disabling ANI\n"); ath_print(ath9k_hw_common(ah), ATH_DBG_ANI, "Disabling ANI\n");
ath9k_hw_disable_mib_counters(ah); ath9k_hw_disable_mib_counters(ah);
REG_WRITE(ah, AR_PHY_ERR_1, 0); REG_WRITE(ah, AR_PHY_ERR_1, 0);
......
drivers/net/wireless/ath/ath9k/ath9k.h
浏览文件 @ c46917bb
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include "rc.h" #include "rc.h"
#include "debug.h" #include "debug.h"
#include "../ath.h" #include "../ath.h"
#include "../debug.h"
struct ath_node; struct ath_node;
......
drivers/net/wireless/ath/ath9k/beacon.c
浏览文件 @ c46917bb
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
static int ath_beaconq_config(struct ath_softc *sc) static int ath_beaconq_config(struct ath_softc *sc)
{ {
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_tx_queue_info qi; struct ath9k_tx_queue_info qi;
ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
...@@ -42,7 +43,7 @@ static int ath_beaconq_config(struct ath_softc *sc) ...@@ -42,7 +43,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
} }
if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Unable to update h/w beacon queue parameters\n"); "Unable to update h/w beacon queue parameters\n");
return 0; return 0;
} else { } else {
...@@ -119,6 +120,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, ...@@ -119,6 +120,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
{ {
struct ath_wiphy *aphy = hw->priv; struct ath_wiphy *aphy = hw->priv;
struct ath_softc *sc = aphy->sc; struct ath_softc *sc = aphy->sc;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_buf *bf; struct ath_buf *bf;
struct ath_vif *avp; struct ath_vif *avp;
struct sk_buff *skb; struct sk_buff *skb;
...@@ -172,7 +174,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, ...@@ -172,7 +174,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
dev_kfree_skb_any(skb); dev_kfree_skb_any(skb);
bf->bf_mpdu = NULL; bf->bf_mpdu = NULL;
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n"); ath_print(common, ATH_DBG_FATAL,
"dma_mapping_error on beaconing\n");
return NULL; return NULL;
} }
...@@ -192,7 +195,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, ...@@ -192,7 +195,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
if (skb && cabq_depth) { if (skb && cabq_depth) {
if (sc->nvifs > 1) { if (sc->nvifs > 1) {
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, ath_print(common, ATH_DBG_BEACON,
"Flushing previous cabq traffic\n"); "Flushing previous cabq traffic\n");
ath_draintxq(sc, cabq, false); ath_draintxq(sc, cabq, false);
} }
...@@ -216,6 +219,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, ...@@ -216,6 +219,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
struct ieee80211_vif *vif) struct ieee80211_vif *vif)
{ {
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_buf *bf; struct ath_buf *bf;
struct ath_vif *avp; struct ath_vif *avp;
struct sk_buff *skb; struct sk_buff *skb;
...@@ -233,7 +237,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, ...@@ -233,7 +237,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
/* NB: caller is known to have already stopped tx dma */ /* NB: caller is known to have already stopped tx dma */
ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr); ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
ath9k_hw_txstart(ah, sc->beacon.beaconq); ath9k_hw_txstart(ah, sc->beacon.beaconq);
DPRINTF(ah, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n", ath_print(common, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc); sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
} }
...@@ -252,6 +256,7 @@ int ath_beaconq_setup(struct ath_hw *ah) ...@@ -252,6 +256,7 @@ int ath_beaconq_setup(struct ath_hw *ah)
int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
{ {
struct ath_softc *sc = aphy->sc; struct ath_softc *sc = aphy->sc;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_vif *avp; struct ath_vif *avp;
struct ath_buf *bf; struct ath_buf *bf;
struct sk_buff *skb; struct sk_buff *skb;
...@@ -309,7 +314,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) ...@@ -309,7 +314,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
/* NB: the beacon data buffer must be 32-bit aligned. */ /* NB: the beacon data buffer must be 32-bit aligned. */
skb = ieee80211_beacon_get(sc->hw, vif); skb = ieee80211_beacon_get(sc->hw, vif);
if (skb == NULL) { if (skb == NULL) {
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "cannot get skb\n"); ath_print(common, ATH_DBG_BEACON, "cannot get skb\n");
return -ENOMEM; return -ENOMEM;
} }
...@@ -333,8 +338,9 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) ...@@ -333,8 +338,9 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
tsfadjust = intval * avp->av_bslot / ATH_BCBUF; tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, ath_print(common, ATH_DBG_BEACON,
"stagger beacons, bslot %d intval %u tsfadjust %llu\n", "stagger beacons, bslot %d intval "
"%u tsfadjust %llu\n",
avp->av_bslot, intval, (unsigned long long)tsfadjust); avp->av_bslot, intval, (unsigned long long)tsfadjust);
((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
...@@ -349,7 +355,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif) ...@@ -349,7 +355,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
dev_kfree_skb_any(skb); dev_kfree_skb_any(skb);
bf->bf_mpdu = NULL; bf->bf_mpdu = NULL;
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"dma_mapping_error on beacon alloc\n"); "dma_mapping_error on beacon alloc\n");
return -ENOMEM; return -ENOMEM;
} }
...@@ -386,6 +392,7 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -386,6 +392,7 @@ void ath_beacon_tasklet(unsigned long data)
{ {
struct ath_softc *sc = (struct ath_softc *)data; struct ath_softc *sc = (struct ath_softc *)data;
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_buf *bf = NULL; struct ath_buf *bf = NULL;
struct ieee80211_vif *vif; struct ieee80211_vif *vif;
struct ath_wiphy *aphy; struct ath_wiphy *aphy;
...@@ -405,11 +412,11 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -405,11 +412,11 @@ void ath_beacon_tasklet(unsigned long data)
sc->beacon.bmisscnt++; sc->beacon.bmisscnt++;
if (sc->beacon.bmisscnt < BSTUCK_THRESH) { if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, ath_print(common, ATH_DBG_BEACON,
"missed %u consecutive beacons\n", "missed %u consecutive beacons\n",
sc->beacon.bmisscnt); sc->beacon.bmisscnt);
} else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, ath_print(common, ATH_DBG_BEACON,
"beacon is officially stuck\n"); "beacon is officially stuck\n");
sc->sc_flags |= SC_OP_TSF_RESET; sc->sc_flags |= SC_OP_TSF_RESET;
ath_reset(sc, false); ath_reset(sc, false);
...@@ -419,7 +426,7 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -419,7 +426,7 @@ void ath_beacon_tasklet(unsigned long data)
} }
if (sc->beacon.bmisscnt != 0) { if (sc->beacon.bmisscnt != 0) {
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, ath_print(common, ATH_DBG_BEACON,
"resume beacon xmit after %u misses\n", "resume beacon xmit after %u misses\n",
sc->beacon.bmisscnt); sc->beacon.bmisscnt);
sc->beacon.bmisscnt = 0; sc->beacon.bmisscnt = 0;
...@@ -447,7 +454,7 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -447,7 +454,7 @@ void ath_beacon_tasklet(unsigned long data)
vif = sc->beacon.bslot[slot]; vif = sc->beacon.bslot[slot];
aphy = sc->beacon.bslot_aphy[slot]; aphy = sc->beacon.bslot_aphy[slot];
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, ath_print(common, ATH_DBG_BEACON,
"slot %d [tsf %llu tsftu %u intval %u] vif %p\n", "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
slot, tsf, tsftu, intval, vif); slot, tsf, tsftu, intval, vif);
...@@ -490,7 +497,7 @@ void ath_beacon_tasklet(unsigned long data) ...@@ -490,7 +497,7 @@ void ath_beacon_tasklet(unsigned long data)
* are still pending on the queue. * are still pending on the queue.
*/ */
if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) { if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"beacon queue %u did not stop?\n", sc->beacon.beaconq); "beacon queue %u did not stop?\n", sc->beacon.beaconq);
} }
...@@ -568,6 +575,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc, ...@@ -568,6 +575,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
static void ath_beacon_config_sta(struct ath_softc *sc, static void ath_beacon_config_sta(struct ath_softc *sc,
struct ath_beacon_config *conf) struct ath_beacon_config *conf)
{ {
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath9k_beacon_state bs; struct ath9k_beacon_state bs;
int dtimperiod, dtimcount, sleepduration; int dtimperiod, dtimcount, sleepduration;
int cfpperiod, cfpcount; int cfpperiod, cfpcount;
...@@ -664,8 +672,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc, ...@@ -664,8 +672,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
/* TSF out of range threshold fixed at 1 second */ /* TSF out of range threshold fixed at 1 second */
bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, ath_print(common, ATH_DBG_BEACON,
"bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
bs.bs_bmissthreshold, bs.bs_sleepduration, bs.bs_bmissthreshold, bs.bs_sleepduration,
bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
...@@ -682,6 +690,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc, ...@@ -682,6 +690,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
struct ath_beacon_config *conf, struct ath_beacon_config *conf,
struct ieee80211_vif *vif) struct ieee80211_vif *vif)
{ {
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
u64 tsf; u64 tsf;
u32 tsftu, intval, nexttbtt; u32 tsftu, intval, nexttbtt;
...@@ -702,7 +711,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc, ...@@ -702,7 +711,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
nexttbtt += intval; nexttbtt += intval;
} while (nexttbtt < tsftu); } while (nexttbtt < tsftu);
DPRINTF(sc->sc_ah, ATH_DBG_BEACON, ath_print(common, ATH_DBG_BEACON,
"IBSS nexttbtt %u intval %u (%u)\n", "IBSS nexttbtt %u intval %u (%u)\n",
nexttbtt, intval, conf->beacon_interval); nexttbtt, intval, conf->beacon_interval);
...@@ -732,6 +741,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc, ...@@ -732,6 +741,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
{ {
struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
enum nl80211_iftype iftype; enum nl80211_iftype iftype;
/* Setup the beacon configuration parameters */ /* Setup the beacon configuration parameters */
...@@ -772,7 +782,7 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif) ...@@ -772,7 +782,7 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
ath_beacon_config_sta(sc, cur_conf); ath_beacon_config_sta(sc, cur_conf);
break; break;
default: default:
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, ath_print(common, ATH_DBG_CONFIG,
"Unsupported beaconing mode\n"); "Unsupported beaconing mode\n");
return; return;
} }
......
drivers/net/wireless/ath/ath9k/calib.c
浏览文件 @ c46917bb
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
*/ */
#include "ath9k.h" #include "ath9k.h"
#include "hw.h"
/* We can tune this as we go by monitoring really low values */ /* We can tune this as we go by monitoring really low values */
#define ATH9K_NF_TOO_LOW -60 #define ATH9K_NF_TOO_LOW -60
...@@ -26,7 +27,7 @@ ...@@ -26,7 +27,7 @@
static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
{ {
if (nf > ATH9K_NF_TOO_LOW) { if (nf > ATH9K_NF_TOO_LOW) {
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
"noise floor value detected (%d) is " "noise floor value detected (%d) is "
"lower than what we think is a " "lower than what we think is a "
"reasonable value (%d)\n", "reasonable value (%d)\n",
...@@ -89,6 +90,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h, ...@@ -89,6 +90,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
static void ath9k_hw_do_getnf(struct ath_hw *ah, static void ath9k_hw_do_getnf(struct ath_hw *ah,
int16_t nfarray[NUM_NF_READINGS]) int16_t nfarray[NUM_NF_READINGS])
{ {
struct ath_common *common = ath9k_hw_common(ah);
int16_t nf; int16_t nf;
if (AR_SREV_9280_10_OR_LATER(ah)) if (AR_SREV_9280_10_OR_LATER(ah))
...@@ -98,7 +100,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, ...@@ -98,7 +100,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"NF calibrated [ctl] [chain 0] is %d\n", nf); "NF calibrated [ctl] [chain 0] is %d\n", nf);
nfarray[0] = nf; nfarray[0] = nf;
...@@ -112,7 +114,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, ...@@ -112,7 +114,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"NF calibrated [ctl] [chain 1] is %d\n", nf); "NF calibrated [ctl] [chain 1] is %d\n", nf);
nfarray[1] = nf; nfarray[1] = nf;
...@@ -121,7 +123,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, ...@@ -121,7 +123,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
AR_PHY_CH2_MINCCA_PWR); AR_PHY_CH2_MINCCA_PWR);
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"NF calibrated [ctl] [chain 2] is %d\n", nf); "NF calibrated [ctl] [chain 2] is %d\n", nf);
nfarray[2] = nf; nfarray[2] = nf;
} }
...@@ -136,7 +138,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, ...@@ -136,7 +138,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"NF calibrated [ext] [chain 0] is %d\n", nf); "NF calibrated [ext] [chain 0] is %d\n", nf);
nfarray[3] = nf; nfarray[3] = nf;
...@@ -150,7 +152,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, ...@@ -150,7 +152,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"NF calibrated [ext] [chain 1] is %d\n", nf); "NF calibrated [ext] [chain 1] is %d\n", nf);
nfarray[4] = nf; nfarray[4] = nf;
...@@ -159,7 +161,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, ...@@ -159,7 +161,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
AR_PHY_CH2_EXT_MINCCA_PWR); AR_PHY_CH2_EXT_MINCCA_PWR);
if (nf & 0x100) if (nf & 0x100)
nf = 0 - ((nf ^ 0x1ff) + 1); nf = 0 - ((nf ^ 0x1ff) + 1);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"NF calibrated [ext] [chain 2] is %d\n", nf); "NF calibrated [ext] [chain 2] is %d\n", nf);
nfarray[5] = nf; nfarray[5] = nf;
} }
...@@ -188,6 +190,8 @@ static bool getNoiseFloorThresh(struct ath_hw *ah, ...@@ -188,6 +190,8 @@ static bool getNoiseFloorThresh(struct ath_hw *ah,
static void ath9k_hw_setup_calibration(struct ath_hw *ah, static void ath9k_hw_setup_calibration(struct ath_hw *ah,
struct ath9k_cal_list *currCal) struct ath9k_cal_list *currCal)
{ {
struct ath_common *common = ath9k_hw_common(ah);
REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
currCal->calData->calCountMax); currCal->calData->calCountMax);
...@@ -195,22 +199,22 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah, ...@@ -195,22 +199,22 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah,
switch (currCal->calData->calType) { switch (currCal->calData->calType) {
case IQ_MISMATCH_CAL: case IQ_MISMATCH_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"starting IQ Mismatch Calibration\n"); "starting IQ Mismatch Calibration\n");
break; break;
case ADC_GAIN_CAL: case ADC_GAIN_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"starting ADC Gain Calibration\n"); "starting ADC Gain Calibration\n");
break; break;
case ADC_DC_CAL: case ADC_DC_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"starting ADC DC Calibration\n"); "starting ADC DC Calibration\n");
break; break;
case ADC_DC_INIT_CAL: case ADC_DC_INIT_CAL:
REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"starting Init ADC DC Calibration\n"); "starting Init ADC DC Calibration\n");
break; break;
} }
...@@ -304,7 +308,7 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah) ...@@ -304,7 +308,7 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
ah->totalIqCorrMeas[i] += ah->totalIqCorrMeas[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
ah->cal_samples, i, ah->totalPowerMeasI[i], ah->cal_samples, i, ah->totalPowerMeasI[i],
ah->totalPowerMeasQ[i], ah->totalPowerMeasQ[i],
...@@ -326,7 +330,7 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) ...@@ -326,7 +330,7 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
ah->totalAdcQEvenPhase[i] += ah->totalAdcQEvenPhase[i] +=
REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
"%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
"oddq=0x%08x; evenq=0x%08x;\n", "oddq=0x%08x; evenq=0x%08x;\n",
ah->cal_samples, i, ah->cal_samples, i,
...@@ -351,7 +355,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) ...@@ -351,7 +355,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
ah->totalAdcDcOffsetQEvenPhase[i] += ah->totalAdcDcOffsetQEvenPhase[i] +=
(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
"%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
"oddq=0x%08x; evenq=0x%08x;\n", "oddq=0x%08x; evenq=0x%08x;\n",
ah->cal_samples, i, ah->cal_samples, i,
...@@ -364,6 +368,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) ...@@ -364,6 +368,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
{ {
struct ath_common *common = ath9k_hw_common(ah);
u32 powerMeasQ, powerMeasI, iqCorrMeas; u32 powerMeasQ, powerMeasI, iqCorrMeas;
u32 qCoffDenom, iCoffDenom; u32 qCoffDenom, iCoffDenom;
int32_t qCoff, iCoff; int32_t qCoff, iCoff;
...@@ -374,11 +379,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) ...@@ -374,11 +379,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
powerMeasQ = ah->totalPowerMeasQ[i]; powerMeasQ = ah->totalPowerMeasQ[i];
iqCorrMeas = ah->totalIqCorrMeas[i]; iqCorrMeas = ah->totalIqCorrMeas[i];
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Starting IQ Cal and Correction for Chain %d\n", "Starting IQ Cal and Correction for Chain %d\n",
i); i);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Orignal: Chn %diq_corr_meas = 0x%08x\n", "Orignal: Chn %diq_corr_meas = 0x%08x\n",
i, ah->totalIqCorrMeas[i]); i, ah->totalIqCorrMeas[i]);
...@@ -389,11 +394,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) ...@@ -389,11 +394,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
iqCorrNeg = 1; iqCorrNeg = 1;
} }
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
DPRINTF(ah, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
iqCorrNeg); iqCorrNeg);
iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
...@@ -402,13 +407,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) ...@@ -402,13 +407,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
if (powerMeasQ != 0) { if (powerMeasQ != 0) {
iCoff = iqCorrMeas / iCoffDenom; iCoff = iqCorrMeas / iCoffDenom;
qCoff = powerMeasI / qCoffDenom - 64; qCoff = powerMeasI / qCoffDenom - 64;
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d iCoff = 0x%08x\n", i, iCoff); "Chn %d iCoff = 0x%08x\n", i, iCoff);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d qCoff = 0x%08x\n", i, qCoff); "Chn %d qCoff = 0x%08x\n", i, qCoff);
iCoff = iCoff & 0x3f; iCoff = iCoff & 0x3f;
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"New: Chn %d iCoff = 0x%08x\n", i, iCoff); "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
if (iqCorrNeg == 0x0) if (iqCorrNeg == 0x0)
iCoff = 0x40 - iCoff; iCoff = 0x40 - iCoff;
...@@ -418,7 +423,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) ...@@ -418,7 +423,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
else if (qCoff <= -16) else if (qCoff <= -16)
qCoff = 16; qCoff = 16;
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d : iCoff = 0x%x qCoff = 0x%x\n", "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
i, iCoff, qCoff); i, iCoff, qCoff);
...@@ -428,7 +433,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) ...@@ -428,7 +433,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
qCoff); qCoff);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"IQ Cal and Correction done for Chain %d\n", "IQ Cal and Correction done for Chain %d\n",
i); i);
} }
...@@ -440,6 +445,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) ...@@ -440,6 +445,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
{ {
struct ath_common *common = ath9k_hw_common(ah);
u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
u32 qGainMismatch, iGainMismatch, val, i; u32 qGainMismatch, iGainMismatch, val, i;
...@@ -449,19 +455,19 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -449,19 +455,19 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
qOddMeasOffset = ah->totalAdcQOddPhase[i]; qOddMeasOffset = ah->totalAdcQOddPhase[i];
qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Starting ADC Gain Cal for Chain %d\n", i); "Starting ADC Gain Cal for Chain %d\n", i);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_odd_i = 0x%08x\n", i, "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
iOddMeasOffset); iOddMeasOffset);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_even_i = 0x%08x\n", i, "Chn %d pwr_meas_even_i = 0x%08x\n", i,
iEvenMeasOffset); iEvenMeasOffset);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_odd_q = 0x%08x\n", i, "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
qOddMeasOffset); qOddMeasOffset);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_even_q = 0x%08x\n", i, "Chn %d pwr_meas_even_q = 0x%08x\n", i,
qEvenMeasOffset); qEvenMeasOffset);
...@@ -473,10 +479,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -473,10 +479,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
((qOddMeasOffset * 32) / ((qOddMeasOffset * 32) /
qEvenMeasOffset) & 0x3f; qEvenMeasOffset) & 0x3f;
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d gain_mismatch_i = 0x%08x\n", i, "Chn %d gain_mismatch_i = 0x%08x\n", i,
iGainMismatch); iGainMismatch);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d gain_mismatch_q = 0x%08x\n", i, "Chn %d gain_mismatch_q = 0x%08x\n", i,
qGainMismatch); qGainMismatch);
...@@ -485,7 +491,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -485,7 +491,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
val |= (qGainMismatch) | (iGainMismatch << 6); val |= (qGainMismatch) | (iGainMismatch << 6);
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"ADC Gain Cal done for Chain %d\n", i); "ADC Gain Cal done for Chain %d\n", i);
} }
} }
...@@ -497,6 +503,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -497,6 +503,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
{ {
struct ath_common *common = ath9k_hw_common(ah);
u32 iOddMeasOffset, iEvenMeasOffset, val, i; u32 iOddMeasOffset, iEvenMeasOffset, val, i;
int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
const struct ath9k_percal_data *calData = const struct ath9k_percal_data *calData =
...@@ -510,19 +517,19 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -510,19 +517,19 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Starting ADC DC Offset Cal for Chain %d\n", i); "Starting ADC DC Offset Cal for Chain %d\n", i);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_odd_i = %d\n", i, "Chn %d pwr_meas_odd_i = %d\n", i,
iOddMeasOffset); iOddMeasOffset);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_even_i = %d\n", i, "Chn %d pwr_meas_even_i = %d\n", i,
iEvenMeasOffset); iEvenMeasOffset);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_odd_q = %d\n", i, "Chn %d pwr_meas_odd_q = %d\n", i,
qOddMeasOffset); qOddMeasOffset);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d pwr_meas_even_q = %d\n", i, "Chn %d pwr_meas_even_q = %d\n", i,
qEvenMeasOffset); qEvenMeasOffset);
...@@ -531,10 +538,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -531,10 +538,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
numSamples) & 0x1ff; numSamples) & 0x1ff;
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d dc_offset_mismatch_i = 0x%08x\n", i, "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
iDcMismatch); iDcMismatch);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Chn %d dc_offset_mismatch_q = 0x%08x\n", i, "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
qDcMismatch); qDcMismatch);
...@@ -543,7 +550,7 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -543,7 +550,7 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
val |= (qDcMismatch << 12) | (iDcMismatch << 21); val |= (qDcMismatch << 12) | (iDcMismatch << 21);
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"ADC DC Offset Cal done for Chain %d\n", i); "ADC DC Offset Cal done for Chain %d\n", i);
} }
...@@ -555,7 +562,8 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) ...@@ -555,7 +562,8 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
/* This is done for the currently configured channel */ /* This is done for the currently configured channel */
bool ath9k_hw_reset_calvalid(struct ath_hw *ah) bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
{ {
struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; struct ath_common *common = ath9k_hw_common(ah);
struct ieee80211_conf *conf = &common->hw->conf;
struct ath9k_cal_list *currCal = ah->cal_list_curr; struct ath9k_cal_list *currCal = ah->cal_list_curr;
if (!ah->curchan) if (!ah->curchan)
...@@ -568,7 +576,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) ...@@ -568,7 +576,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
return true; return true;
if (currCal->calState != CAL_DONE) { if (currCal->calState != CAL_DONE) {
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Calibration state incorrect, %d\n", "Calibration state incorrect, %d\n",
currCal->calState); currCal->calState);
return true; return true;
...@@ -577,7 +585,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) ...@@ -577,7 +585,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
return true; return true;
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"Resetting Cal %d state for channel %u\n", "Resetting Cal %d state for channel %u\n",
currCal->calData->calType, conf->channel->center_freq); currCal->calData->calType, conf->channel->center_freq);
...@@ -665,6 +673,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -665,6 +673,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
int16_t ath9k_hw_getnf(struct ath_hw *ah, int16_t ath9k_hw_getnf(struct ath_hw *ah,
struct ath9k_channel *chan) struct ath9k_channel *chan)
{ {
struct ath_common *common = ath9k_hw_common(ah);
int16_t nf, nfThresh; int16_t nf, nfThresh;
int16_t nfarray[NUM_NF_READINGS] = { 0 }; int16_t nfarray[NUM_NF_READINGS] = { 0 };
struct ath9k_nfcal_hist *h; struct ath9k_nfcal_hist *h;
...@@ -672,7 +681,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah, ...@@ -672,7 +681,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
chan->channelFlags &= (~CHANNEL_CW_INT); chan->channelFlags &= (~CHANNEL_CW_INT);
if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"NF did not complete in calibration window\n"); "NF did not complete in calibration window\n");
nf = 0; nf = 0;
chan->rawNoiseFloor = nf; chan->rawNoiseFloor = nf;
...@@ -682,7 +691,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah, ...@@ -682,7 +691,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
nf = nfarray[0]; nf = nfarray[0];
if (getNoiseFloorThresh(ah, c->band, &nfThresh) if (getNoiseFloorThresh(ah, c->band, &nfThresh)
&& nf > nfThresh) { && nf > nfThresh) {
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"noise floor failed detected; " "noise floor failed detected; "
"detected %d, threshold %d\n", "detected %d, threshold %d\n",
nf, nfThresh); nf, nfThresh);
...@@ -875,7 +884,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah) ...@@ -875,7 +884,7 @@ static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)
static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset) static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
{ {
struct ath_common *common = ath9k_hw_common(ah);
u32 regVal; u32 regVal;
int i, offset, offs_6_1, offs_0; int i, offset, offs_6_1, offs_0;
u32 ccomp_org, reg_field; u32 ccomp_org, reg_field;
...@@ -889,7 +898,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset) ...@@ -889,7 +898,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
{ 0x7838, 0 }, { 0x7838, 0 },
}; };
DPRINTF(ah, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
/* PA CAL is not needed for high power solution */ /* PA CAL is not needed for high power solution */
if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
...@@ -1039,6 +1048,8 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, ...@@ -1039,6 +1048,8 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
{ {
struct ath_common *common = ath9k_hw_common(ah);
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
if (IS_CHAN_HT20(chan)) { if (IS_CHAN_HT20(chan)) {
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
...@@ -1049,7 +1060,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -1049,7 +1060,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
DPRINTF(ah, ATH_DBG_CALIBRATE, "offset " ath_print(common, ATH_DBG_CALIBRATE, "offset "
"calibration failed to complete in " "calibration failed to complete in "
"1ms; noisy ??\n"); "1ms; noisy ??\n");
return false; return false;
...@@ -1064,7 +1075,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -1064,7 +1075,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
0, AH_WAIT_TIMEOUT)) { 0, AH_WAIT_TIMEOUT)) {
DPRINTF(ah, ATH_DBG_CALIBRATE, "offset calibration " ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
"failed to complete in 1ms; noisy ??\n"); "failed to complete in 1ms; noisy ??\n");
return false; return false;
} }
...@@ -1078,6 +1089,8 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -1078,6 +1089,8 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
{ {
struct ath_common *common = ath9k_hw_common(ah);
if (AR_SREV_9285_12_OR_LATER(ah)) { if (AR_SREV_9285_12_OR_LATER(ah)) {
if (!ar9285_clc(ah, chan)) if (!ar9285_clc(ah, chan))
return false; return false;
...@@ -1098,9 +1111,9 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -1098,9 +1111,9 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
/* Poll for offset calibration complete */ /* Poll for offset calibration complete */
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
0, AH_WAIT_TIMEOUT)) { 0, AH_WAIT_TIMEOUT)) {
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"offset calibration failed to complete in 1ms; " "offset calibration failed to "
"noisy environment?\n"); "complete in 1ms; noisy environment?\n");
return false; return false;
} }
...@@ -1128,19 +1141,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -1128,19 +1141,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
INIT_CAL(&ah->adcgain_caldata); INIT_CAL(&ah->adcgain_caldata);
INSERT_CAL(ah, &ah->adcgain_caldata); INSERT_CAL(ah, &ah->adcgain_caldata);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"enabling ADC Gain Calibration.\n"); "enabling ADC Gain Calibration.\n");
} }
if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
INIT_CAL(&ah->adcdc_caldata); INIT_CAL(&ah->adcdc_caldata);
INSERT_CAL(ah, &ah->adcdc_caldata); INSERT_CAL(ah, &ah->adcdc_caldata);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"enabling ADC DC Calibration.\n"); "enabling ADC DC Calibration.\n");
} }
if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
INIT_CAL(&ah->iq_caldata); INIT_CAL(&ah->iq_caldata);
INSERT_CAL(ah, &ah->iq_caldata); INSERT_CAL(ah, &ah->iq_caldata);
DPRINTF(ah, ATH_DBG_CALIBRATE, ath_print(common, ATH_DBG_CALIBRATE,
"enabling IQ Calibration.\n"); "enabling IQ Calibration.\n");
} }
......
drivers/net/wireless/ath/ath9k/calib.h
浏览文件 @ c46917bb
...@@ -17,6 +17,8 @@ ...@@ -17,6 +17,8 @@
#ifndef CALIB_H #ifndef CALIB_H
#define CALIB_H #define CALIB_H
#include "hw.h"
extern const struct ath9k_percal_data iq_cal_multi_sample; extern const struct ath9k_percal_data iq_cal_multi_sample;
extern const struct ath9k_percal_data iq_cal_single_sample; extern const struct ath9k_percal_data iq_cal_single_sample;
extern const struct ath9k_percal_data adc_gain_cal_multi_sample; extern const struct ath9k_percal_data adc_gain_cal_multi_sample;
......
drivers/net/wireless/ath/ath9k/debug.c
浏览文件 @ c46917bb
...@@ -18,26 +18,11 @@ ...@@ -18,26 +18,11 @@
#include "ath9k.h" #include "ath9k.h"
static unsigned int ath9k_debug = DBG_DEFAULT; static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
module_param_named(debug, ath9k_debug, uint, 0); module_param_named(debug, ath9k_debug, uint, 0);
static struct dentry *ath9k_debugfs_root; static struct dentry *ath9k_debugfs_root;
void DPRINTF(struct ath_hw *ah, int dbg_mask, const char *fmt, ...)
{
if (!ah->ah_sc)
return;
if (ah->ah_sc->debug.debug_mask & dbg_mask) {
va_list args;
va_start(args, fmt);
printk(KERN_DEBUG "ath9k: ");
vprintk(fmt, args);
va_end(args);
}
}
static int ath9k_debugfs_open(struct inode *inode, struct file *file) static int ath9k_debugfs_open(struct inode *inode, struct file *file)
{ {
file->private_data = inode->i_private; file->private_data = inode->i_private;
...@@ -48,10 +33,11 @@ static ssize_t read_file_debug(struct file *file, char __user *user_buf, ...@@ -48,10 +33,11 @@ static ssize_t read_file_debug(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos) size_t count, loff_t *ppos)
{ {
struct ath_softc *sc = file->private_data; struct ath_softc *sc = file->private_data;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
char buf[32]; char buf[32];
unsigned int len; unsigned int len;
len = snprintf(buf, sizeof(buf), "0x%08x\n", sc->debug.debug_mask); len = snprintf(buf, sizeof(buf), "0x%08x\n", common->debug_mask);
return simple_read_from_buffer(user_buf, count, ppos, buf, len); return simple_read_from_buffer(user_buf, count, ppos, buf, len);
} }
...@@ -59,6 +45,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf, ...@@ -59,6 +45,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
size_t count, loff_t *ppos) size_t count, loff_t *ppos)
{ {
struct ath_softc *sc = file->private_data; struct ath_softc *sc = file->private_data;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
unsigned long mask; unsigned long mask;
char buf[32]; char buf[32];
ssize_t len; ssize_t len;
...@@ -71,7 +58,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf, ...@@ -71,7 +58,7 @@ static ssize_t write_file_debug(struct file *file, const char __user *user_buf,
if (strict_strtoul(buf, 0, &mask)) if (strict_strtoul(buf, 0, &mask))
return -EINVAL; return -EINVAL;
sc->debug.debug_mask = mask; common->debug_mask = mask;
return count; return count;
} }
...@@ -571,8 +558,9 @@ static const struct file_operations fops_xmit = { ...@@ -571,8 +558,9 @@ static const struct file_operations fops_xmit = {
int ath9k_init_debug(struct ath_hw *ah) int ath9k_init_debug(struct ath_hw *ah)
{ {
struct ath_softc *sc = ah->ah_sc; struct ath_softc *sc = ah->ah_sc;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
sc->debug.debug_mask = ath9k_debug; common->debug_mask = ath9k_debug;
if (!ath9k_debugfs_root) if (!ath9k_debugfs_root)
return -ENOENT; return -ENOENT;
......
drivers/net/wireless/ath/ath9k/debug.h
浏览文件 @ c46917bb
...@@ -19,26 +19,6 @@ ...@@ -19,26 +19,6 @@
#include "hw.h" #include "hw.h"
enum ATH_DEBUG {
ATH_DBG_RESET = 0x00000001,
ATH_DBG_QUEUE = 0x00000002,
ATH_DBG_EEPROM = 0x00000004,
ATH_DBG_CALIBRATE = 0x00000008,
ATH_DBG_INTERRUPT = 0x00000010,
ATH_DBG_REGULATORY = 0x00000020,
ATH_DBG_ANI = 0x00000040,
ATH_DBG_XMIT = 0x00000080,
ATH_DBG_BEACON = 0x00000100,
ATH_DBG_CONFIG = 0x00000200,
ATH_DBG_FATAL = 0x00000400,
ATH_DBG_PS = 0x00000800,
ATH_DBG_HWTIMER = 0x00001000,
ATH_DBG_BTCOEX = 0x00002000,
ATH_DBG_ANY = 0xffffffff
};
#define DBG_DEFAULT (ATH_DBG_FATAL)
struct ath_txq; struct ath_txq;
struct ath_buf; struct ath_buf;
...@@ -142,7 +122,6 @@ struct ath_stats { ...@@ -142,7 +122,6 @@ struct ath_stats {
}; };
struct ath9k_debug { struct ath9k_debug {
int debug_mask;
struct dentry *debugfs_phy; struct dentry *debugfs_phy;
struct dentry *debugfs_debug; struct dentry *debugfs_debug;
struct dentry *debugfs_dma; struct dentry *debugfs_dma;
...@@ -153,7 +132,6 @@ struct ath9k_debug { ...@@ -153,7 +132,6 @@ struct ath9k_debug {
struct ath_stats stats; struct ath_stats stats;
}; };
void DPRINTF(struct ath_hw *ah, int dbg_mask, const char *fmt, ...);
int ath9k_init_debug(struct ath_hw *ah); int ath9k_init_debug(struct ath_hw *ah);
void ath9k_exit_debug(struct ath_hw *ah); void ath9k_exit_debug(struct ath_hw *ah);
...@@ -168,11 +146,6 @@ void ath_debug_stat_retries(struct ath_softc *sc, int rix, ...@@ -168,11 +146,6 @@ void ath_debug_stat_retries(struct ath_softc *sc, int rix,
#else #else
static inline void DPRINTF(struct ath_hw *ah, int dbg_mask,
const char *fmt, ...)
{
}
static inline int ath9k_init_debug(struct ath_hw *ah) static inline int ath9k_init_debug(struct ath_hw *ah)
{ {
return 0; return 0;
......
drivers/net/wireless/ath/ath9k/eeprom_4k.c
浏览文件 @ c46917bb
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
*/ */
#include "ath9k.h" #include "ath9k.h"
#include "hw.h"
static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
{ {
...@@ -29,19 +30,20 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) ...@@ -29,19 +30,20 @@ static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
{ {
#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
struct ath_common *common = ath9k_hw_common(ah);
u16 *eep_data = (u16 *)&ah->eeprom.map4k; u16 *eep_data = (u16 *)&ah->eeprom.map4k;
int addr, eep_start_loc = 0; int addr, eep_start_loc = 0;
eep_start_loc = 64; eep_start_loc = 64;
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"Reading from EEPROM, not flash\n"); "Reading from EEPROM, not flash\n");
} }
for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"Unable to read eeprom region \n"); "Unable to read eeprom region \n");
return false; return false;
} }
...@@ -55,6 +57,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) ...@@ -55,6 +57,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
{ {
#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
struct ath_common *common = ath9k_hw_common(ah);
struct ar5416_eeprom_4k *eep = struct ar5416_eeprom_4k *eep =
(struct ar5416_eeprom_4k *) &ah->eeprom.map4k; (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
u16 *eepdata, temp, magic, magic2; u16 *eepdata, temp, magic, magic2;
...@@ -66,12 +69,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -66,12 +69,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
&magic)) { &magic)) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Reading Magic # failed\n"); "Reading Magic # failed\n");
return false; return false;
} }
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"Read Magic = 0x%04X\n", magic); "Read Magic = 0x%04X\n", magic);
if (magic != AR5416_EEPROM_MAGIC) { if (magic != AR5416_EEPROM_MAGIC) {
...@@ -87,7 +90,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -87,7 +90,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
eepdata++; eepdata++;
} }
} else { } else {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Invalid EEPROM Magic. " "Invalid EEPROM Magic. "
"endianness mismatch.\n"); "endianness mismatch.\n");
return -EINVAL; return -EINVAL;
...@@ -95,7 +98,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -95,7 +98,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
} }
} }
DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n", ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
need_swap ? "True" : "False"); need_swap ? "True" : "False");
if (need_swap) if (need_swap)
...@@ -117,7 +120,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -117,7 +120,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
u32 integer; u32 integer;
u16 word; u16 word;
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"EEPROM Endianness is not native.. Changing\n"); "EEPROM Endianness is not native.. Changing\n");
word = swab16(eep->baseEepHeader.length); word = swab16(eep->baseEepHeader.length);
...@@ -160,7 +163,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) ...@@ -160,7 +163,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Bad EEPROM checksum 0x%x or revision 0x%04x\n", "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
sum, ah->eep_ops->get_eeprom_ver(ah)); sum, ah->eep_ops->get_eeprom_ver(ah));
return -EINVAL; return -EINVAL;
...@@ -385,6 +388,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, ...@@ -385,6 +388,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
struct ath9k_channel *chan, struct ath9k_channel *chan,
int16_t *pTxPowerIndexOffset) int16_t *pTxPowerIndexOffset)
{ {
struct ath_common *common = ath9k_hw_common(ah);
struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
struct cal_data_per_freq_4k *pRawDataset; struct cal_data_per_freq_4k *pRawDataset;
u8 *pCalBChans = NULL; u8 *pCalBChans = NULL;
...@@ -470,11 +474,11 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, ...@@ -470,11 +474,11 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
((pdadcValues[4 * j + 3] & 0xFF) << 24); ((pdadcValues[4 * j + 3] & 0xFF) << 24);
REG_WRITE(ah, regOffset, reg32); REG_WRITE(ah, regOffset, reg32);
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"PDADC (%d,%4x): %4.4x %8.8x\n", "PDADC (%d,%4x): %4.4x %8.8x\n",
i, regChainOffset, regOffset, i, regChainOffset, regOffset,
reg32); reg32);
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"PDADC: Chain %d | " "PDADC: Chain %d | "
"PDADC %3d Value %3d | " "PDADC %3d Value %3d | "
"PDADC %3d Value %3d | " "PDADC %3d Value %3d | "
...@@ -1148,10 +1152,11 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) ...@@ -1148,10 +1152,11 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
{ {
#define EEP_MAP4K_SPURCHAN \ #define EEP_MAP4K_SPURCHAN \
(ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
struct ath_common *common = ath9k_hw_common(ah);
u16 spur_val = AR_NO_SPUR; u16 spur_val = AR_NO_SPUR;
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Getting spur idx %d is2Ghz. %d val %x\n", "Getting spur idx %d is2Ghz. %d val %x\n",
i, is2GHz, ah->config.spurchans[i][is2GHz]); i, is2GHz, ah->config.spurchans[i][is2GHz]);
...@@ -1160,7 +1165,7 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) ...@@ -1160,7 +1165,7 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
break; break;
case SPUR_ENABLE_IOCTL: case SPUR_ENABLE_IOCTL:
spur_val = ah->config.spurchans[i][is2GHz]; spur_val = ah->config.spurchans[i][is2GHz];
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Getting spur val from new loc. %d\n", spur_val); "Getting spur val from new loc. %d\n", spur_val);
break; break;
case SPUR_ENABLE_EEPROM: case SPUR_ENABLE_EEPROM:
......
drivers/net/wireless/ath/ath9k/eeprom_9287.c
浏览文件 @ c46917bb
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
*/ */
#include "ath9k.h" #include "ath9k.h"
#include "hw.h"
static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
{ {
...@@ -29,19 +30,20 @@ static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah) ...@@ -29,19 +30,20 @@ static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah)
static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah) static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
{ {
struct ar9287_eeprom *eep = &ah->eeprom.map9287; struct ar9287_eeprom *eep = &ah->eeprom.map9287;
struct ath_common *common = ath9k_hw_common(ah);
u16 *eep_data; u16 *eep_data;
int addr, eep_start_loc = AR9287_EEP_START_LOC; int addr, eep_start_loc = AR9287_EEP_START_LOC;
eep_data = (u16 *)eep; eep_data = (u16 *)eep;
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"Reading from EEPROM, not flash\n"); "Reading from EEPROM, not flash\n");
} }
for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16); for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
addr++) { addr++) {
if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"Unable to read eeprom region \n"); "Unable to read eeprom region \n");
return false; return false;
} }
...@@ -57,16 +59,17 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah) ...@@ -57,16 +59,17 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
int i, addr; int i, addr;
bool need_swap = false; bool need_swap = false;
struct ar9287_eeprom *eep = &ah->eeprom.map9287; struct ar9287_eeprom *eep = &ah->eeprom.map9287;
struct ath_common *common = ath9k_hw_common(ah);
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
if (!ath9k_hw_nvram_read if (!ath9k_hw_nvram_read
(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Reading Magic # failed\n"); "Reading Magic # failed\n");
return false; return false;
} }
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"Read Magic = 0x%04X\n", magic); "Read Magic = 0x%04X\n", magic);
if (magic != AR5416_EEPROM_MAGIC) { if (magic != AR5416_EEPROM_MAGIC) {
magic2 = swab16(magic); magic2 = swab16(magic);
...@@ -83,14 +86,14 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah) ...@@ -83,14 +86,14 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
eepdata++; eepdata++;
} }
} else { } else {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Invalid EEPROM Magic. " "Invalid EEPROM Magic. "
"endianness mismatch.\n"); "endianness mismatch.\n");
return -EINVAL; return -EINVAL;
} }
} }
} }
DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
"True" : "False"); "True" : "False");
if (need_swap) if (need_swap)
...@@ -148,7 +151,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah) ...@@ -148,7 +151,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
|| ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Bad EEPROM checksum 0x%x or revision 0x%04x\n", "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
sum, ah->eep_ops->get_eeprom_ver(ah)); sum, ah->eep_ops->get_eeprom_ver(ah));
return -EINVAL; return -EINVAL;
...@@ -436,6 +439,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah, ...@@ -436,6 +439,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
struct ath9k_channel *chan, struct ath9k_channel *chan,
int16_t *pTxPowerIndexOffset) int16_t *pTxPowerIndexOffset)
{ {
struct ath_common *common = ath9k_hw_common(ah);
struct cal_data_per_freq_ar9287 *pRawDataset; struct cal_data_per_freq_ar9287 *pRawDataset;
struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
u8 *pCalBChans = NULL; u8 *pCalBChans = NULL;
...@@ -564,12 +568,13 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah, ...@@ -564,12 +568,13 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
& 0xFF) << 24) ; & 0xFF) << 24) ;
REG_WRITE(ah, regOffset, reg32); REG_WRITE(ah, regOffset, reg32);
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"PDADC (%d,%4x): %4.4x %8.8x\n", "PDADC (%d,%4x): %4.4x "
"%8.8x\n",
i, regChainOffset, regOffset, i, regChainOffset, regOffset,
reg32); reg32);
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"PDADC: Chain %d | " "PDADC: Chain %d | "
"PDADC %3d Value %3d | " "PDADC %3d Value %3d | "
"PDADC %3d Value %3d | " "PDADC %3d Value %3d | "
...@@ -831,6 +836,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah, ...@@ -831,6 +836,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
{ {
#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6
#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10
struct ath_common *common = ath9k_hw_common(ah);
struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
...@@ -966,7 +972,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah, ...@@ -966,7 +972,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
INCREASE_MAXPOW_BY_THREE_CHAIN; INCREASE_MAXPOW_BY_THREE_CHAIN;
break; break;
default: default:
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"Invalid chainmask configuration\n"); "Invalid chainmask configuration\n");
break; break;
} }
...@@ -1138,9 +1144,10 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah, ...@@ -1138,9 +1144,10 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
{ {
#define EEP_MAP9287_SPURCHAN \ #define EEP_MAP9287_SPURCHAN \
(ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
struct ath_common *common = ath9k_hw_common(ah);
u16 spur_val = AR_NO_SPUR; u16 spur_val = AR_NO_SPUR;
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Getting spur idx %d is2Ghz. %d val %x\n", "Getting spur idx %d is2Ghz. %d val %x\n",
i, is2GHz, ah->config.spurchans[i][is2GHz]); i, is2GHz, ah->config.spurchans[i][is2GHz]);
...@@ -1149,7 +1156,7 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah, ...@@ -1149,7 +1156,7 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
break; break;
case SPUR_ENABLE_IOCTL: case SPUR_ENABLE_IOCTL:
spur_val = ah->config.spurchans[i][is2GHz]; spur_val = ah->config.spurchans[i][is2GHz];
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Getting spur val from new loc. %d\n", spur_val); "Getting spur val from new loc. %d\n", spur_val);
break; break;
case SPUR_ENABLE_EEPROM: case SPUR_ENABLE_EEPROM:
......
drivers/net/wireless/ath/ath9k/eeprom_def.c
浏览文件 @ c46917bb
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
*/ */
#include "ath9k.h" #include "ath9k.h"
#include "hw.h"
static void ath9k_get_txgain_index(struct ath_hw *ah, static void ath9k_get_txgain_index(struct ath_hw *ah,
struct ath9k_channel *chan, struct ath9k_channel *chan,
...@@ -95,7 +96,7 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) ...@@ -95,7 +96,7 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
eep_data)) { eep_data)) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
"Unable to read eeprom region\n"); "Unable to read eeprom region\n");
return false; return false;
} }
...@@ -109,18 +110,19 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) ...@@ -109,18 +110,19 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
{ {
struct ar5416_eeprom_def *eep = struct ar5416_eeprom_def *eep =
(struct ar5416_eeprom_def *) &ah->eeprom.def; (struct ar5416_eeprom_def *) &ah->eeprom.def;
struct ath_common *common = ath9k_hw_common(ah);
u16 *eepdata, temp, magic, magic2; u16 *eepdata, temp, magic, magic2;
u32 sum = 0, el; u32 sum = 0, el;
bool need_swap = false; bool need_swap = false;
int i, addr, size; int i, addr, size;
if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
DPRINTF(ah, ATH_DBG_FATAL, "Reading Magic # failed\n"); ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
return false; return false;
} }
if (!ath9k_hw_use_flash(ah)) { if (!ath9k_hw_use_flash(ah)) {
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"Read Magic = 0x%04X\n", magic); "Read Magic = 0x%04X\n", magic);
if (magic != AR5416_EEPROM_MAGIC) { if (magic != AR5416_EEPROM_MAGIC) {
...@@ -137,7 +139,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) ...@@ -137,7 +139,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
eepdata++; eepdata++;
} }
} else { } else {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Invalid EEPROM Magic. " "Invalid EEPROM Magic. "
"Endianness mismatch.\n"); "Endianness mismatch.\n");
return -EINVAL; return -EINVAL;
...@@ -145,7 +147,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) ...@@ -145,7 +147,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
} }
} }
DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n", ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
need_swap ? "True" : "False"); need_swap ? "True" : "False");
if (need_swap) if (need_swap)
...@@ -167,7 +169,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) ...@@ -167,7 +169,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
u32 integer, j; u32 integer, j;
u16 word; u16 word;
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"EEPROM Endianness is not native.. Changing.\n"); "EEPROM Endianness is not native.. Changing.\n");
word = swab16(eep->baseEepHeader.length); word = swab16(eep->baseEepHeader.length);
...@@ -214,7 +216,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) ...@@ -214,7 +216,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Bad EEPROM checksum 0x%x or revision 0x%04x\n", "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
sum, ah->eep_ops->get_eeprom_ver(ah)); sum, ah->eep_ops->get_eeprom_ver(ah));
return -EINVAL; return -EINVAL;
...@@ -746,7 +748,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, ...@@ -746,7 +748,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x) #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
#define SM_PDGAIN_B(x, y) \ #define SM_PDGAIN_B(x, y) \
SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y) SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
struct ath_common *common = ath9k_hw_common(ah);
struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
struct cal_data_per_freq *pRawDataset; struct cal_data_per_freq *pRawDataset;
u8 *pCalBChans = NULL; u8 *pCalBChans = NULL;
...@@ -870,11 +872,11 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, ...@@ -870,11 +872,11 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
((pdadcValues[4 * j + 3] & 0xFF) << 24); ((pdadcValues[4 * j + 3] & 0xFF) << 24);
REG_WRITE(ah, regOffset, reg32); REG_WRITE(ah, regOffset, reg32);
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"PDADC (%d,%4x): %4.4x %8.8x\n", "PDADC (%d,%4x): %4.4x %8.8x\n",
i, regChainOffset, regOffset, i, regChainOffset, regOffset,
reg32); reg32);
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(common, ATH_DBG_EEPROM,
"PDADC: Chain %d | PDADC %3d " "PDADC: Chain %d | PDADC %3d "
"Value %3d | PDADC %3d Value %3d | " "Value %3d | PDADC %3d Value %3d | "
"PDADC %3d Value %3d | PDADC %3d " "PDADC %3d Value %3d | PDADC %3d "
...@@ -1311,7 +1313,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah, ...@@ -1311,7 +1313,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
break; break;
default: default:
DPRINTF(ah, ATH_DBG_EEPROM, ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
"Invalid chainmask configuration\n"); "Invalid chainmask configuration\n");
break; break;
} }
...@@ -1349,10 +1351,11 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) ...@@ -1349,10 +1351,11 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
{ {
#define EEP_DEF_SPURCHAN \ #define EEP_DEF_SPURCHAN \
(ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
struct ath_common *common = ath9k_hw_common(ah);
u16 spur_val = AR_NO_SPUR; u16 spur_val = AR_NO_SPUR;
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Getting spur idx %d is2Ghz. %d val %x\n", "Getting spur idx %d is2Ghz. %d val %x\n",
i, is2GHz, ah->config.spurchans[i][is2GHz]); i, is2GHz, ah->config.spurchans[i][is2GHz]);
...@@ -1361,7 +1364,7 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) ...@@ -1361,7 +1364,7 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
break; break;
case SPUR_ENABLE_IOCTL: case SPUR_ENABLE_IOCTL:
spur_val = ah->config.spurchans[i][is2GHz]; spur_val = ah->config.spurchans[i][is2GHz];
DPRINTF(ah, ATH_DBG_ANI, ath_print(common, ATH_DBG_ANI,
"Getting spur val from new loc. %d\n", spur_val); "Getting spur val from new loc. %d\n", spur_val);
break; break;
case SPUR_ENABLE_EEPROM: case SPUR_ENABLE_EEPROM:
......
drivers/net/wireless/ath/ath9k/hw.c
浏览文件 @ c46917bb
此差异已折叠。
drivers/net/wireless/ath/ath9k/hw.h
浏览文件 @ c46917bb
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include "btcoex.h" #include "btcoex.h"
#include "../regd.h" #include "../regd.h"
#include "../debug.h"
#define ATHEROS_VENDOR_ID 0x168c #define ATHEROS_VENDOR_ID 0x168c
#define AR5416_DEVID_PCI 0x0023 #define AR5416_DEVID_PCI 0x0023
......
drivers/net/wireless/ath/ath9k/mac.c
浏览文件 @ c46917bb
...@@ -15,11 +15,12 @@ ...@@ -15,11 +15,12 @@
*/ */
#include "ath9k.h" #include "ath9k.h"
#include "hw.h"
static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
struct ath9k_tx_queue_info *qi) struct ath9k_tx_queue_info *qi)
{ {
DPRINTF(ah, ATH_DBG_INTERRUPT, ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
"tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
ah->txok_interrupt_mask, ah->txerr_interrupt_mask, ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
...@@ -47,7 +48,8 @@ void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) ...@@ -47,7 +48,8 @@ void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
void ath9k_hw_txstart(struct ath_hw *ah, u32 q) void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
{ {
DPRINTF(ah, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q); ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
"Enable TXE on queue: %u\n", q);
REG_WRITE(ah, AR_Q_TXE, 1 << q); REG_WRITE(ah, AR_Q_TXE, 1 << q);
} }
...@@ -98,21 +100,21 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) ...@@ -98,21 +100,21 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
{ {
#define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */
#define ATH9K_TIME_QUANTUM 100 /* usec */ #define ATH9K_TIME_QUANTUM 100 /* usec */
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
u32 tsfLow, j, wait; u32 tsfLow, j, wait;
u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah, ATH_DBG_QUEUE, "Stopping TX DMA, " ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
"invalid queue: %u\n", q); "invalid queue: %u\n", q);
return false; return false;
} }
qi = &ah->txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah, ATH_DBG_QUEUE, "Stopping TX DMA, " ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
"inactive queue: %u\n", q); "inactive queue: %u\n", q);
return false; return false;
} }
...@@ -126,7 +128,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) ...@@ -126,7 +128,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
} }
if (ath9k_hw_numtxpending(ah, q)) { if (ath9k_hw_numtxpending(ah, q)) {
DPRINTF(ah, ATH_DBG_QUEUE, ath_print(common, ATH_DBG_QUEUE,
"%s: Num of pending TX Frames %d on Q %d\n", "%s: Num of pending TX Frames %d on Q %d\n",
__func__, ath9k_hw_numtxpending(ah, q), q); __func__, ath9k_hw_numtxpending(ah, q), q);
...@@ -142,7 +144,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) ...@@ -142,7 +144,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
break; break;
DPRINTF(ah, ATH_DBG_QUEUE, ath_print(common, ATH_DBG_QUEUE,
"TSF has moved while trying to set " "TSF has moved while trying to set "
"quiet time TSF: 0x%08x\n", tsfLow); "quiet time TSF: 0x%08x\n", tsfLow);
} }
...@@ -155,7 +157,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) ...@@ -155,7 +157,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
wait = wait_time; wait = wait_time;
while (ath9k_hw_numtxpending(ah, q)) { while (ath9k_hw_numtxpending(ah, q)) {
if ((--wait) == 0) { if ((--wait) == 0) {
DPRINTF(ah, ATH_DBG_QUEUE, ath_print(common, ATH_DBG_QUEUE,
"Failed to stop TX DMA in 100 " "Failed to stop TX DMA in 100 "
"msec after killing last frame\n"); "msec after killing last frame\n");
break; break;
...@@ -445,23 +447,24 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, ...@@ -445,23 +447,24 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
const struct ath9k_tx_queue_info *qinfo) const struct ath9k_tx_queue_info *qinfo)
{ {
u32 cw; u32 cw;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah, ATH_DBG_QUEUE, "Set TXQ properties, " ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
"invalid queue: %u\n", q); "invalid queue: %u\n", q);
return false; return false;
} }
qi = &ah->txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah, ATH_DBG_QUEUE, "Set TXQ properties, " ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
"inactive queue: %u\n", q); "inactive queue: %u\n", q);
return false; return false;
} }
DPRINTF(ah, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
qi->tqi_ver = qinfo->tqi_ver; qi->tqi_ver = qinfo->tqi_ver;
qi->tqi_subtype = qinfo->tqi_subtype; qi->tqi_subtype = qinfo->tqi_subtype;
...@@ -514,18 +517,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, ...@@ -514,18 +517,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
struct ath9k_tx_queue_info *qinfo) struct ath9k_tx_queue_info *qinfo)
{ {
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah, ATH_DBG_QUEUE, "Get TXQ properties, " ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
"invalid queue: %u\n", q); "invalid queue: %u\n", q);
return false; return false;
} }
qi = &ah->txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah, ATH_DBG_QUEUE, "Get TXQ properties, " ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
"inactive queue: %u\n", q); "inactive queue: %u\n", q);
return false; return false;
} }
...@@ -551,6 +555,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, ...@@ -551,6 +555,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
const struct ath9k_tx_queue_info *qinfo) const struct ath9k_tx_queue_info *qinfo)
{ {
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
int q; int q;
...@@ -574,22 +579,22 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, ...@@ -574,22 +579,22 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
ATH9K_TX_QUEUE_INACTIVE) ATH9K_TX_QUEUE_INACTIVE)
break; break;
if (q == pCap->total_queues) { if (q == pCap->total_queues) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"No available TX queue\n"); "No available TX queue\n");
return -1; return -1;
} }
break; break;
default: default:
DPRINTF(ah, ATH_DBG_FATAL, "Invalid TX queue type: %u\n", ath_print(common, ATH_DBG_FATAL,
type); "Invalid TX queue type: %u\n", type);
return -1; return -1;
} }
DPRINTF(ah, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
qi = &ah->txq[q]; qi = &ah->txq[q];
if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"TX queue: %u already active\n", q); "TX queue: %u already active\n", q);
return -1; return -1;
} }
...@@ -617,21 +622,22 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, ...@@ -617,21 +622,22 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
{ {
struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah, ATH_DBG_QUEUE, "Release TXQ, " ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
"invalid queue: %u\n", q); "invalid queue: %u\n", q);
return false; return false;
} }
qi = &ah->txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah, ATH_DBG_QUEUE, "Release TXQ, " ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
"inactive queue: %u\n", q); "inactive queue: %u\n", q);
return false; return false;
} }
DPRINTF(ah, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
ah->txok_interrupt_mask &= ~(1 << q); ah->txok_interrupt_mask &= ~(1 << q);
...@@ -647,24 +653,25 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) ...@@ -647,24 +653,25 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
{ {
struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_hw_capabilities *pCap = &ah->caps;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_channel *chan = ah->curchan; struct ath9k_channel *chan = ah->curchan;
struct ath9k_tx_queue_info *qi; struct ath9k_tx_queue_info *qi;
u32 cwMin, chanCwMin, value; u32 cwMin, chanCwMin, value;
if (q >= pCap->total_queues) { if (q >= pCap->total_queues) {
DPRINTF(ah, ATH_DBG_QUEUE, "Reset TXQ, " ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
"invalid queue: %u\n", q); "invalid queue: %u\n", q);
return false; return false;
} }
qi = &ah->txq[q]; qi = &ah->txq[q];
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
DPRINTF(ah, ATH_DBG_QUEUE, "Reset TXQ, " ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
"inactive queue: %u\n", q); "inactive queue: %u\n", q);
return true; return true;
} }
DPRINTF(ah, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
if (chan && IS_CHAN_B(chan)) if (chan && IS_CHAN_B(chan))
...@@ -911,8 +918,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) ...@@ -911,8 +918,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
AR_DIAG_RX_ABORT)); AR_DIAG_RX_ABORT));
reg = REG_READ(ah, AR_OBS_BUS_1); reg = REG_READ(ah, AR_OBS_BUS_1);
DPRINTF(ah, ATH_DBG_FATAL, ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
"RX failed to go idle in 10 ms RXSM=0x%x\n", reg); "RX failed to go idle in 10 ms RXSM=0x%x\n",
reg);
return false; return false;
} }
...@@ -954,7 +962,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah) ...@@ -954,7 +962,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
{ {
#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ #define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
#define AH_RX_TIME_QUANTUM 100 /* usec */ #define AH_RX_TIME_QUANTUM 100 /* usec */
struct ath_common *common = ath9k_hw_common(ah);
int i; int i;
REG_WRITE(ah, AR_CR, AR_CR_RXD); REG_WRITE(ah, AR_CR, AR_CR_RXD);
...@@ -967,7 +975,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah) ...@@ -967,7 +975,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
} }
if (i == 0) { if (i == 0) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"DMA failed to stop in %d ms " "DMA failed to stop in %d ms "
"AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
AH_RX_STOP_DMA_TIMEOUT / 1000, AH_RX_STOP_DMA_TIMEOUT / 1000,
......
drivers/net/wireless/ath/ath9k/phy.c
浏览文件 @ c46917bb
...@@ -26,6 +26,7 @@ ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, ...@@ -26,6 +26,7 @@ ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
bool bool
ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
{ {
struct ath_common *common = ath9k_hw_common(ah);
u32 channelSel = 0; u32 channelSel = 0;
u32 bModeSynth = 0; u32 bModeSynth = 0;
u32 aModeRefSel = 0; u32 aModeRefSel = 0;
...@@ -46,7 +47,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -46,7 +47,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
channelSel = ((freq - 704) * 2 - 3040) / 10; channelSel = ((freq - 704) * 2 - 3040) / 10;
bModeSynth = 1; bModeSynth = 1;
} else { } else {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Invalid channel %u MHz\n", freq); "Invalid channel %u MHz\n", freq);
return false; return false;
} }
...@@ -79,7 +80,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -79,7 +80,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
aModeRefSel = ath9k_hw_reverse_bits(1, 2); aModeRefSel = ath9k_hw_reverse_bits(1, 2);
} else { } else {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Invalid channel %u MHz\n", freq); "Invalid channel %u MHz\n", freq);
return false; return false;
} }
...@@ -285,6 +286,8 @@ ath9k_hw_rf_free(struct ath_hw *ah) ...@@ -285,6 +286,8 @@ ath9k_hw_rf_free(struct ath_hw *ah)
bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
{ {
struct ath_common *common = ath9k_hw_common(ah);
if (!AR_SREV_9280_10_OR_LATER(ah)) { if (!AR_SREV_9280_10_OR_LATER(ah)) {
ah->analogBank0Data = ah->analogBank0Data =
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
...@@ -315,7 +318,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) ...@@ -315,7 +318,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
|| ah->analogBank6Data == NULL || ah->analogBank6Data == NULL
|| ah->analogBank6TPCData == NULL || ah->analogBank6TPCData == NULL
|| ah->analogBank7Data == NULL) { || ah->analogBank7Data == NULL) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Cannot allocate RF banks\n"); "Cannot allocate RF banks\n");
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
...@@ -326,7 +329,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) ...@@ -326,7 +329,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
ah->iniAddac.ia_rows * ah->iniAddac.ia_rows *
ah->iniAddac.ia_columns), GFP_KERNEL); ah->iniAddac.ia_columns), GFP_KERNEL);
if (ah->addac5416_21 == NULL) { if (ah->addac5416_21 == NULL) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Cannot allocate addac5416_21\n"); "Cannot allocate addac5416_21\n");
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
...@@ -336,7 +339,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) ...@@ -336,7 +339,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
kzalloc((sizeof(u32) * kzalloc((sizeof(u32) *
ah->iniBank6.ia_rows), GFP_KERNEL); ah->iniBank6.ia_rows), GFP_KERNEL);
if (ah->bank6Temp == NULL) { if (ah->bank6Temp == NULL) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Cannot allocate bank6Temp\n"); "Cannot allocate bank6Temp\n");
*status = -ENOMEM; *status = -ENOMEM;
return false; return false;
......
drivers/net/wireless/ath/ath9k/rc.c
浏览文件 @ c46917bb
...@@ -1160,6 +1160,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc, ...@@ -1160,6 +1160,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
bool is_cw_40) bool is_cw_40)
{ {
int mode = 0; int mode = 0;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
switch(band) { switch(band) {
case IEEE80211_BAND_2GHZ: case IEEE80211_BAND_2GHZ:
...@@ -1177,13 +1178,13 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc, ...@@ -1177,13 +1178,13 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
mode = ATH9K_MODE_11NA_HT40PLUS; mode = ATH9K_MODE_11NA_HT40PLUS;
break; break;
default: default:
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Invalid band\n"); ath_print(common, ATH_DBG_CONFIG, "Invalid band\n");
return NULL; return NULL;
} }
BUG_ON(mode >= ATH9K_MODE_MAX); BUG_ON(mode >= ATH9K_MODE_MAX);
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, ath_print(common, ATH_DBG_CONFIG,
"Choosing rate table for mode: %d\n", mode); "Choosing rate table for mode: %d\n", mode);
return sc->hw_rate_table[mode]; return sc->hw_rate_table[mode];
} }
...@@ -1195,11 +1196,12 @@ static void ath_rc_init(struct ath_softc *sc, ...@@ -1195,11 +1196,12 @@ static void ath_rc_init(struct ath_softc *sc,
const struct ath_rate_table *rate_table) const struct ath_rate_table *rate_table)
{ {
struct ath_rateset *rateset = &ath_rc_priv->neg_rates; struct ath_rateset *rateset = &ath_rc_priv->neg_rates;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates; u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates;
u8 i, j, k, hi = 0, hthi = 0; u8 i, j, k, hi = 0, hthi = 0;
if (!rate_table) { if (!rate_table) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Rate table not initialized\n"); "Rate table not initialized\n");
return; return;
} }
...@@ -1263,7 +1265,7 @@ static void ath_rc_init(struct ath_softc *sc, ...@@ -1263,7 +1265,7 @@ static void ath_rc_init(struct ath_softc *sc,
ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
sc->cur_rate_table = rate_table; sc->cur_rate_table = rate_table;
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, ath_print(common, ATH_DBG_CONFIG,
"RC Initialized with capabilities: 0x%x\n", "RC Initialized with capabilities: 0x%x\n",
ath_rc_priv->ht_cap); ath_rc_priv->ht_cap);
} }
...@@ -1441,7 +1443,7 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband, ...@@ -1441,7 +1443,7 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
oper_cw40, oper_sgi40); oper_cw40, oper_sgi40);
ath_rc_init(sc, priv_sta, sband, sta, rate_table); ath_rc_init(sc, priv_sta, sband, sta, rate_table);
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
"Operating HT Bandwidth changed to: %d\n", "Operating HT Bandwidth changed to: %d\n",
sc->hw->conf.channel_type); sc->hw->conf.channel_type);
} }
...@@ -1466,7 +1468,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp ...@@ -1466,7 +1468,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp); rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
if (!rate_priv) { if (!rate_priv) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
"Unable to allocate private rc structure\n"); "Unable to allocate private rc structure\n");
return NULL; return NULL;
} }
......
drivers/net/wireless/ath/ath9k/recv.c
浏览文件 @ c46917bb
...@@ -309,7 +309,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) ...@@ -309,7 +309,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
min(common->cachelsz, (u16)64)); min(common->cachelsz, (u16)64));
DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
common->cachelsz, sc->rx.bufsize); common->cachelsz, sc->rx.bufsize);
/* Initialize rx descriptors */ /* Initialize rx descriptors */
...@@ -317,7 +317,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) ...@@ -317,7 +317,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
"rx", nbufs, 1); "rx", nbufs, 1);
if (error != 0) { if (error != 0) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"failed to allocate rx descriptors: %d\n", error); "failed to allocate rx descriptors: %d\n", error);
goto err; goto err;
} }
...@@ -337,7 +337,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) ...@@ -337,7 +337,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
bf->bf_buf_addr))) { bf->bf_buf_addr))) {
dev_kfree_skb_any(skb); dev_kfree_skb_any(skb);
bf->bf_mpdu = NULL; bf->bf_mpdu = NULL;
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"dma_mapping_error() on RX init\n"); "dma_mapping_error() on RX init\n");
error = -ENOMEM; error = -ENOMEM;
goto err; goto err;
...@@ -543,7 +543,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) ...@@ -543,7 +543,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
if (sc->sc_flags & SC_OP_BEACON_SYNC) { if (sc->sc_flags & SC_OP_BEACON_SYNC) {
sc->sc_flags &= ~SC_OP_BEACON_SYNC; sc->sc_flags &= ~SC_OP_BEACON_SYNC;
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Reconfigure Beacon timers based on " ath_print(common, ATH_DBG_PS,
"Reconfigure Beacon timers based on "
"timestamp from the AP\n"); "timestamp from the AP\n");
ath_beacon_config(sc, NULL); ath_beacon_config(sc, NULL);
} }
...@@ -556,7 +557,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) ...@@ -556,7 +557,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
* a backup trigger for returning into NETWORK SLEEP state, * a backup trigger for returning into NETWORK SLEEP state,
* so we are waiting for it as well. * so we are waiting for it as well.
*/ */
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Received DTIM beacon indicating " ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
"buffered broadcast/multicast frame(s)\n"); "buffered broadcast/multicast frame(s)\n");
sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON;
return; return;
...@@ -569,13 +570,15 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) ...@@ -569,13 +570,15 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
* been delivered. * been delivered.
*/ */
sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
DPRINTF(sc->sc_ah, ATH_DBG_PS, "PS wait for CAB frames timed out\n"); ath_print(common, ATH_DBG_PS,
"PS wait for CAB frames timed out\n");
} }
} }
static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
{ {
struct ieee80211_hdr *hdr; struct ieee80211_hdr *hdr;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
hdr = (struct ieee80211_hdr *)skb->data; hdr = (struct ieee80211_hdr *)skb->data;
...@@ -593,14 +596,15 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) ...@@ -593,14 +596,15 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
* point. * point.
*/ */
sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
DPRINTF(sc->sc_ah, ATH_DBG_PS, "All PS CAB frames received, back to " ath_print(common, ATH_DBG_PS,
"sleep\n"); "All PS CAB frames received, back to sleep\n");
} else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) &&
!is_multicast_ether_addr(hdr->addr1) && !is_multicast_ether_addr(hdr->addr1) &&
!ieee80211_has_morefrags(hdr->frame_control)) { !ieee80211_has_morefrags(hdr->frame_control)) {
sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA;
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Going back to sleep after having " ath_print(common, ATH_DBG_PS,
"received PS-Poll data (0x%x)\n", "Going back to sleep after having received "
"PS-Poll data (0x%x)\n",
sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_CAB |
SC_OP_WAIT_FOR_PSPOLL_DATA | SC_OP_WAIT_FOR_PSPOLL_DATA |
...@@ -816,7 +820,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) ...@@ -816,7 +820,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
bf->bf_buf_addr))) { bf->bf_buf_addr))) {
dev_kfree_skb_any(requeue_skb); dev_kfree_skb_any(requeue_skb);
bf->bf_mpdu = NULL; bf->bf_mpdu = NULL;
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"dma_mapping_error() on RX\n"); "dma_mapping_error() on RX\n");
ath_rx_send_to_mac80211(sc, skb, &rx_status); ath_rx_send_to_mac80211(sc, skb, &rx_status);
break; break;
......
drivers/net/wireless/ath/ath9k/xmit.c
浏览文件 @ c46917bb
...@@ -815,6 +815,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc, ...@@ -815,6 +815,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
{ {
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath9k_tx_queue_info qi; struct ath9k_tx_queue_info qi;
int qnum; int qnum;
...@@ -854,7 +855,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) ...@@ -854,7 +855,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
return NULL; return NULL;
} }
if (qnum >= ARRAY_SIZE(sc->tx.txq)) { if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
DPRINTF(ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"qnum %u out of range, max %u!\n", "qnum %u out of range, max %u!\n",
qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
ath9k_hw_releasetxqueue(ah, qnum); ath9k_hw_releasetxqueue(ah, qnum);
...@@ -884,7 +885,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) ...@@ -884,7 +885,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
switch (qtype) { switch (qtype) {
case ATH9K_TX_QUEUE_DATA: case ATH9K_TX_QUEUE_DATA:
if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
"HAL AC %u out of range, max %zu!\n", "HAL AC %u out of range, max %zu!\n",
haltype, ARRAY_SIZE(sc->tx.hwq_map)); haltype, ARRAY_SIZE(sc->tx.hwq_map));
return -1; return -1;
...@@ -914,7 +915,7 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) ...@@ -914,7 +915,7 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
spin_lock_bh(&txq->axq_lock); spin_lock_bh(&txq->axq_lock);
if (txq->axq_depth >= (ATH_TXBUF - 20)) { if (txq->axq_depth >= (ATH_TXBUF - 20)) {
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
"TX queue: %d is full, depth: %d\n", "TX queue: %d is full, depth: %d\n",
qnum, txq->axq_depth); qnum, txq->axq_depth);
ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
...@@ -955,7 +956,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum, ...@@ -955,7 +956,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
qi.tqi_readyTime = qinfo->tqi_readyTime; qi.tqi_readyTime = qinfo->tqi_readyTime;
if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
"Unable to update hardware queue %u!\n", qnum); "Unable to update hardware queue %u!\n", qnum);
error = -EIO; error = -EIO;
} else { } else {
...@@ -1055,6 +1056,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) ...@@ -1055,6 +1056,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
{ {
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_txq *txq; struct ath_txq *txq;
int i, npend = 0; int i, npend = 0;
...@@ -1076,12 +1078,13 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) ...@@ -1076,12 +1078,13 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
if (npend) { if (npend) {
int r; int r;
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); ath_print(common, ATH_DBG_XMIT,
"Unable to stop TxDMA. Reset HAL!\n");
spin_lock_bh(&sc->sc_resetlock); spin_lock_bh(&sc->sc_resetlock);
r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
if (r) if (r)
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Unable to reset hardware; reset status %d\n", "Unable to reset hardware; reset status %d\n",
r); r);
spin_unlock_bh(&sc->sc_resetlock); spin_unlock_bh(&sc->sc_resetlock);
...@@ -1147,7 +1150,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype) ...@@ -1147,7 +1150,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
struct ath_txq *txq; struct ath_txq *txq;
if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
"HAL AC %u out of range, max %zu!\n", "HAL AC %u out of range, max %zu!\n",
haltype, ARRAY_SIZE(sc->tx.hwq_map)); haltype, ARRAY_SIZE(sc->tx.hwq_map));
return 0; return 0;
...@@ -1172,6 +1175,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, ...@@ -1172,6 +1175,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
struct list_head *head) struct list_head *head)
{ {
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_buf *bf; struct ath_buf *bf;
/* /*
...@@ -1188,17 +1192,17 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, ...@@ -1188,17 +1192,17 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
txq->axq_depth++; txq->axq_depth++;
txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
DPRINTF(sc->sc_ah, ATH_DBG_QUEUE, ath_print(common, ATH_DBG_QUEUE,
"qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
if (txq->axq_link == NULL) { if (txq->axq_link == NULL) {
ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, ath_print(common, ATH_DBG_XMIT,
"TXDP[%u] = %llx (%p)\n", "TXDP[%u] = %llx (%p)\n",
txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
} else { } else {
*txq->axq_link = bf->bf_daddr; *txq->axq_link = bf->bf_daddr;
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
txq->axq_qnum, txq->axq_link, txq->axq_qnum, txq->axq_link,
ito64(bf->bf_daddr), bf->bf_desc); ito64(bf->bf_daddr), bf->bf_desc);
} }
...@@ -1587,7 +1591,7 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, ...@@ -1587,7 +1591,7 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
bf->bf_mpdu = NULL; bf->bf_mpdu = NULL;
kfree(tx_info_priv); kfree(tx_info_priv);
tx_info->rate_driver_data[0] = NULL; tx_info->rate_driver_data[0] = NULL;
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
"dma_mapping_error() on TX\n"); "dma_mapping_error() on TX\n");
return -ENOMEM; return -ENOMEM;
} }
...@@ -1670,12 +1674,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, ...@@ -1670,12 +1674,13 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
{ {
struct ath_wiphy *aphy = hw->priv; struct ath_wiphy *aphy = hw->priv;
struct ath_softc *sc = aphy->sc; struct ath_softc *sc = aphy->sc;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_buf *bf; struct ath_buf *bf;
int r; int r;
bf = ath_tx_get_buffer(sc); bf = ath_tx_get_buffer(sc);
if (!bf) { if (!bf) {
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX buffers are full\n"); ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
return -1; return -1;
} }
...@@ -1683,7 +1688,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, ...@@ -1683,7 +1688,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
if (unlikely(r)) { if (unlikely(r)) {
struct ath_txq *txq = txctl->txq; struct ath_txq *txq = txctl->txq;
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TX mem alloc failure\n"); ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
/* upon ath_tx_processq() this TX queue will be resumed, we /* upon ath_tx_processq() this TX queue will be resumed, we
* guarantee this will happen by knowing beforehand that * guarantee this will happen by knowing beforehand that
...@@ -1713,6 +1718,7 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) ...@@ -1713,6 +1718,7 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
{ {
struct ath_wiphy *aphy = hw->priv; struct ath_wiphy *aphy = hw->priv;
struct ath_softc *sc = aphy->sc; struct ath_softc *sc = aphy->sc;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
int hdrlen, padsize; int hdrlen, padsize;
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
struct ath_tx_control txctl; struct ath_tx_control txctl;
...@@ -1737,7 +1743,7 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) ...@@ -1737,7 +1743,7 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
if (hdrlen & 3) { if (hdrlen & 3) {
padsize = hdrlen % 4; padsize = hdrlen % 4;
if (skb_headroom(skb) < padsize) { if (skb_headroom(skb) < padsize) {
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, ath_print(common, ATH_DBG_XMIT,
"TX CABQ padding failed\n"); "TX CABQ padding failed\n");
dev_kfree_skb_any(skb); dev_kfree_skb_any(skb);
return; return;
...@@ -1748,10 +1754,11 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) ...@@ -1748,10 +1754,11 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
txctl.txq = sc->beacon.cabq; txctl.txq = sc->beacon.cabq;
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); ath_print(common, ATH_DBG_XMIT,
"transmitting CABQ packet, skb: %p\n", skb);
if (ath_tx_start(hw, skb, &txctl) != 0) { if (ath_tx_start(hw, skb, &txctl) != 0) {
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "CABQ TX failed\n"); ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
goto exit; goto exit;
} }
...@@ -1770,10 +1777,11 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, ...@@ -1770,10 +1777,11 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
struct ieee80211_hw *hw = sc->hw; struct ieee80211_hw *hw = sc->hw;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
int hdrlen, padsize; int hdrlen, padsize;
int frame_type = ATH9K_NOT_INTERNAL; int frame_type = ATH9K_NOT_INTERNAL;
DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
if (tx_info_priv) { if (tx_info_priv) {
hw = tx_info_priv->aphy->hw; hw = tx_info_priv->aphy->hw;
...@@ -1807,7 +1815,8 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, ...@@ -1807,7 +1815,8 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
DPRINTF(sc->sc_ah, ATH_DBG_PS, "Going back to sleep after having " ath_print(common, ATH_DBG_PS,
"Going back to sleep after having "
"received TX status (0x%x)\n", "received TX status (0x%x)\n",
sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_CAB |
...@@ -1938,13 +1947,14 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) ...@@ -1938,13 +1947,14 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
{ {
struct ath_hw *ah = sc->sc_ah; struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_buf *bf, *lastbf, *bf_held = NULL; struct ath_buf *bf, *lastbf, *bf_held = NULL;
struct list_head bf_head; struct list_head bf_head;
struct ath_desc *ds; struct ath_desc *ds;
int txok; int txok;
int status; int status;
DPRINTF(ah, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
txq->axq_link); txq->axq_link);
...@@ -2066,7 +2076,8 @@ static void ath_tx_complete_poll_work(struct work_struct *work) ...@@ -2066,7 +2076,8 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
} }
if (needreset) { if (needreset) {
DPRINTF(sc->sc_ah, ATH_DBG_RESET, "tx hung, resetting the chip\n"); ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
"tx hung, resetting the chip\n");
ath_reset(sc, false); ath_reset(sc, false);
} }
...@@ -2095,6 +2106,7 @@ void ath_tx_tasklet(struct ath_softc *sc) ...@@ -2095,6 +2106,7 @@ void ath_tx_tasklet(struct ath_softc *sc)
int ath_tx_init(struct ath_softc *sc, int nbufs) int ath_tx_init(struct ath_softc *sc, int nbufs)
{ {
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
int error = 0; int error = 0;
spin_lock_init(&sc->tx.txbuflock); spin_lock_init(&sc->tx.txbuflock);
...@@ -2102,7 +2114,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs) ...@@ -2102,7 +2114,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
"tx", nbufs, 1); "tx", nbufs, 1);
if (error != 0) { if (error != 0) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Failed to allocate tx descriptors: %d\n", error); "Failed to allocate tx descriptors: %d\n", error);
goto err; goto err;
} }
...@@ -2110,7 +2122,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs) ...@@ -2110,7 +2122,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
"beacon", ATH_BCBUF, 1); "beacon", ATH_BCBUF, 1);
if (error != 0) { if (error != 0) {
DPRINTF(sc->sc_ah, ATH_DBG_FATAL, ath_print(common, ATH_DBG_FATAL,
"Failed to allocate beacon descriptors: %d\n", error); "Failed to allocate beacon descriptors: %d\n", error);
goto err; goto err;
} }
......
drivers/net/wireless/ath/debug.c 0 → 100644
浏览文件 @ c46917bb
/*
* Copyright (c) 2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ath.h"
#include "debug.h"
void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
{
va_list args;
if (likely(!(common->debug_mask & dbg_mask)))
return;
va_start(args, fmt);
printk(KERN_DEBUG "ath: ");
vprintk(fmt, args);
va_end(args);
}
EXPORT_SYMBOL(ath_print);
drivers/net/wireless/ath/debug.h 0 → 100644
浏览文件 @ c46917bb
/*
* Copyright (c) 2008-2009 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef ATH_DEBUG_H
#define ATH_DEBUG_H
#include "ath.h"
/**
* enum ath_debug_level - atheros wireless debug level
*
* @ATH_DBG_RESET: reset processing
* @ATH_DBG_QUEUE: hardware queue management
* @ATH_DBG_EEPROM: eeprom processing
* @ATH_DBG_CALIBRATE: periodic calibration
* @ATH_DBG_INTERRUPT: interrupt processing
* @ATH_DBG_REGULATORY: regulatory processing
* @ATH_DBG_ANI: adaptive noise immunitive processing
* @ATH_DBG_XMIT: basic xmit operation
* @ATH_DBG_BEACON: beacon handling
* @ATH_DBG_CONFIG: configuration of the hardware
* @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
* @ATH_DBG_PS: power save processing
* @ATH_DBG_HWTIMER: hardware timer handling
* @ATH_DBG_BTCOEX: bluetooth coexistance
* @ATH_DBG_ANY: enable all debugging
*
* The debug level is used to control the amount and type of debugging output
* we want to see. Each driver has its own method for enabling debugging and
* modifying debug level states -- but this is typically done through a
* module parameter 'debug' along with a respective 'debug' debugfs file
* entry.
*/
enum ATH_DEBUG {
ATH_DBG_RESET = 0x00000001,
ATH_DBG_QUEUE = 0x00000002,
ATH_DBG_EEPROM = 0x00000004,
ATH_DBG_CALIBRATE = 0x00000008,
ATH_DBG_INTERRUPT = 0x00000010,
ATH_DBG_REGULATORY = 0x00000020,
ATH_DBG_ANI = 0x00000040,
ATH_DBG_XMIT = 0x00000080,
ATH_DBG_BEACON = 0x00000100,
ATH_DBG_CONFIG = 0x00000200,
ATH_DBG_FATAL = 0x00000400,
ATH_DBG_PS = 0x00000800,
ATH_DBG_HWTIMER = 0x00001000,
ATH_DBG_BTCOEX = 0x00002000,
ATH_DBG_ANY = 0xffffffff
};
#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
#ifdef CONFIG_ATH_DEBUG
void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...);
#else
static inline void ath_print(struct ath_common *common,
int dbg_mask,
const char *fmt, ...)
{
}
#endif /* CONFIG_ATH_DEBUG */
#endif /* ATH_DEBUG_H */
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