arm64/mpam: Supplement MPAM MSC register layout definitions

hulk inclusion
category: feature
feature: ARM MPAM support
bugzilla: 48265
CVE: NA

--------------------------------

Memory Partitioning and Monitoring (MPAM) has memory mapped
devices (MSCs) with an identity/configuration page.

Supplement the definitions for these registers as offset
within the page(s).

[Wang ShaoBo: replace tab with space and useful definitions are added]
Signed-off-by: NJames Morse <james.morse@arm.com>
http://www.linux-arm.org/git?p=linux-jm.git;a=patch;h=a9102d227c371ec3cf3913fe735243840a985c18Signed-off-by: NWang ShaoBo <bobo.shaobowang@huawei.com>
Reviewed-by: NXiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: NCheng Jian <cj.chengjian@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NZheng Zengkai <zhengzengkai@huawei.com>

arch/arm64/include/asm/mpam_resource.h

@@ -46,9 +46,11 @@
 #define HAS_PRI_PART        BIT(27)
 #define HAS_IMPL_IDR        BIT(29)
 #define HAS_MSMON           BIT(30)
+#define HAS_PARTID_NRW      BIT(31)
 
 /* MPAMF_IDR */
 #define MPAMF_IDR_PMG_MAX_MASK      ((BIT(8) - 1) << 16)
+#define MPAMF_IDR_PMG_MAX_SHIFT     16
 #define MPAMF_IDR_PARTID_MAX_MASK   (BIT(16) - 1)
 #define MPAMF_IDR_PMG_MAX_GET(v)    ((v & MPAMF_IDR_PMG_MAX_MASK) >> 16)
 #define MPAMF_IDR_PARTID_MAX_GET(v) (v & MPAMF_IDR_PARTID_MAX_MASK)
@@ -57,38 +59,136 @@
 #define MPAMF_IDR_HAS_CPOR_PART(v)  ((v) & HAS_CPOR_PART)
 #define MPAMF_IDR_HAS_MBW_PART(v)   ((v) & HAS_MBW_PART)
 #define MPAMF_IDR_HAS_MSMON(v)      ((v) & HAS_MSMON)
-
-/* MPAMF_x_IDR */
+#define MPAMF_IDR_PARTID_MASK       GENMASK(15, 0)
+#define MPAMF_IDR_PMG_MASK          GENMASK(23, 16)
+#define MPAMF_IDR_PMG_SHIFT         16
+#define MPAMF_IDR_HAS_PARTID_NRW(v) ((v) & HAS_PARTID_NRW)
 #define NUM_MON_MASK                (BIT(16) - 1)
 #define MPAMF_IDR_NUM_MON(v)        ((v) & NUM_MON_MASK)
 
-/* TODO */
-
 #define CPBM_WD_MASK        0xFFFF
 #define CPBM_MASK           0x7FFF
 
 #define BWA_WD              6		/* hard code for P680 */
 #define MBW_MAX_MASK        0xFC00
 #define MBW_MAX_HARDLIM     BIT(31)
+#define MBW_MAX_SET(v)      (MBW_MAX_HARDLIM|((v) << (16 - BWA_WD)))
+#define MBW_MAX_GET(v)      (((v) & MBW_MAX_MASK) >> (16 - BWA_WD))
 
 #define MSMON_MATCH_PMG     BIT(17)
 #define MSMON_MATCH_PARTID  BIT(16)
-
 #define MSMON_CFG_CTL_EN    BIT(31)
-
 #define MSMON_CFG_FLT_SET(r, p)     ((r) << 16|(p))
-
 #define MBWU_SUBTYPE_DEFAULT        (3 << 20)
 #define MSMON_CFG_MBWU_CTL_SET(m)   (BIT(31)|MBWU_SUBTYPE_DEFAULT|(m))
-
 #define MSMON_CFG_CSU_CTL_SET(m)    (BIT(31)|(m))
-
 #define MSMON_CFG_CSU_TYPE          0x43
 #define MSMON_CFG_MBWU_TYPE         0x42
 
-/* [FIXME] hard code for hardlim */
-#define MBW_MAX_SET(v)		(MBW_MAX_HARDLIM|((v) << (16 - BWA_WD)))
-#define MBW_MAX_GET(v)		(((v) & MBW_MAX_MASK) >> (16 - BWA_WD))
+/*
+ * Size of the memory mapped registers: 4K of feature page then 2 x 4K
+ * bitmap registers
+ */
+#define SZ_MPAM_DEVICE  (3 * SZ_4K)
+
+/*
+ * MSMON_CSU - Memory system performance monitor cache storage usage monitor
+ *            register
+ * MSMON_CSU_CAPTURE -  Memory system performance monitor cache storage usage
+ *                     capture register
+ * MSMON_MBWU  - Memory system performance monitor memory bandwidth usage
+ *               monitor register
+ * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage
+ *                     capture register
+ */
+#define MSMON___VALUE          GENMASK(30, 0)
+#define MSMON___NRDY           BIT(31)
+
+/*
+ * MSMON_CAPT_EVNT - Memory system performance monitoring capture event
+ *                  generation register
+ */
+#define MSMON_CAPT_EVNT_NOW    BIT(0)
+/*
+ * MPAMCFG_MBW_MAX SET - temp Hard code
+ */
+#define MPAMCFG_PRI_DSPRI_SHIFT			16
+
+/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
+#define MPAMF_PRI_IDR_HAS_INTPRI        BIT(0)
+#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW   BIT(1)
+#define MPAMF_PRI_IDR_INTPRI_WD_SHIFT   4
+#define MPAMF_PRI_IDR_INTPRI_WD         GENMASK(9, 4)
+#define MPAMF_PRI_IDR_HAS_DSPRI         BIT(16)
+#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW    BIT(17)
+#define MPAMF_PRI_IDR_DSPRI_WD_SHIFT    20
+#define MPAMF_PRI_IDR_DSPRI_WD          GENMASK(25, 20)
+
+/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
+#define MPAMF_CSUMON_IDR_NUM_MON        GENMASK(15, 0)
+#define MPAMF_CSUMON_IDR_HAS_CAPTURE    BIT(31)
+
+/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */
+#define MPAMF_MBWUMON_IDR_NUM_MON       GENMASK(15, 0)
+#define MPAMF_MBWUMON_IDR_HAS_CAPTURE   BIT(31)
+
+/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */
+#define MPAMF_CPOR_IDR_CPBM_WD          GENMASK(15, 0)
+
+/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */
+#define MPAMF_CCAP_IDR_CMAX_WD          GENMASK(5, 0)
+
+/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
+#define MPAMF_MBW_IDR_BWA_WD            GENMASK(5, 0)
+#define MPAMF_MBW_IDR_HAS_MIN           BIT(10)
+#define MPAMF_MBW_IDR_HAS_MAX           BIT(11)
+#define MPAMF_MBW_IDR_HAS_PBM           BIT(12)
+
+#define MPAMF_MBW_IDR_HAS_PROP          BIT(13)
+#define MPAMF_MBW_IDR_WINDWR            BIT(14)
+#define MPAMF_MBW_IDR_BWPBM_WD          GENMASK(28, 16)
+#define MPAMF_MBW_IDR_BWPBM_WD_SHIFT	16
+
+/* MPAMF_PARTID_NRW_IDR - MPAM features partid narrow ID register */
+#define MPAMF_PARTID_NRW_IDR_MASK	 (BIT(16) - 1)
+
+#define MSMON_CFG_CTL_TYPE           GENMASK(7, 0)
+#define MSMON_CFG_CTL_MATCH_PARTID   BIT(16)
+#define MSMON_CFG_CTL_MATCH_PMG      BIT(17)
+#define MSMON_CFG_CTL_SUBTYPE        GENMASK(23, 20)
+#define MSMON_CFG_CTL_SUBTYPE_SHIFT  20
+#define MSMON_CFG_CTL_OFLOW_FRZ      BIT(24)
+#define MSMON_CFG_CTL_OFLOW_INTR     BIT(25)
+#define MSMON_CFG_CTL_OFLOW_STATUS   BIT(26)
+#define MSMON_CFG_CTL_CAPT_RESET     BIT(27)
+#define MSMON_CFG_CTL_CAPT_EVNT      GENMASK(30, 28)
+#define MSMON_CFG_CTL_CAPT_EVNT_SHIFT		28
+#define MSMON_CFG_CTL_EN					BIT(31)
+
+#define MPAMF_IDR_HAS_PRI_PART(v)			(v & BIT(27))
+
+/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
+#define MPAMF_MSMON_IDR_MSMON_CSU               BIT(16)
+#define MPAMF_MSMON_IDR_MSMON_MBWU              BIT(17)
+#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT     BIT(31)
+
+/*
+ * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory
+ *                     bandwidth usage monitor filter register
+ */
+#define MSMON_CFG_MBWU_FLT_PARTID               GENMASK(15, 0)
+#define MSMON_CFG_MBWU_FLT_PMG_SHIFT			16
+#define MSMON_CFG_MBWU_FLT_PMG                  GENMASK(23, 16)
+#define MSMON_CFG_MBWU_TYPE 0x42
+
+/*
+ * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage
+ *                    usage monitor filter register
+ */
+#define MSMON_CFG_CSU_FLT_PARTID		GENMASK(15, 0)
+#define MSMON_CFG_CSU_FLT_PMG			GENMASK(23, 16)
+#define MSMON_CFG_CSU_FLT_PMG_SHIFT		16
+#define MSMON_CFG_CSU_TYPE  0x43
 
 /* hard code for mbw_max max-percentage's cresponding masks */
 #define MBA_MAX_WD 63u