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提交 bc36e655 编写于 作者: J J.R. Mauro 提交者： Greg Kroah-Hartman
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Staging: Clean up sxg driver 

Lindent the rest of the files in drivers/staging/sxg

Signed off by: J.R. Mauro <jrm8005@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 2ae5a6d2
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Showing with 368 addition and 379 deletion
drivers/staging/sxg/sxg_os.h
浏览文件 @ bc36e655
......@@ -44,7 +44,6 @@
#define FALSE (0)
#define TRUE (1)
typedef struct _LIST_ENTRY {
struct _LIST_ENTRY *nle_flink;
struct _LIST_ENTRY *nle_blink;
......@@ -69,8 +68,7 @@ typedef struct _LIST_ENTRY {
/* These two have to be inlined since they return things. */
static __inline PLIST_ENTRY
RemoveHeadList(list_entry *l)
static __inline PLIST_ENTRY RemoveHeadList(list_entry * l)
{
list_entry *f;
list_entry *e;
......@@ -83,8 +81,7 @@ RemoveHeadList(list_entry *l)
return (e);
}
static __inline PLIST_ENTRY
RemoveTailList(list_entry *l)
static __inline PLIST_ENTRY RemoveTailList(list_entry * l)
{
list_entry *b;
list_entry *e;
......@@ -97,7 +94,6 @@ RemoveTailList(list_entry *l)
return (e);
}
#define InsertTailList(l, e) \
do { \
list_entry *b; \
......@@ -120,7 +116,6 @@ RemoveTailList(list_entry *l)
(l)->nle_flink = (e); \
} while (0)
#define ATK_DEBUG 1
#if ATK_DEBUG
......@@ -133,7 +128,6 @@ RemoveTailList(list_entry *l)
#define SLIC_TIMESTAMP(value)
#endif
/****************** SXG DEFINES *****************************************/
#ifdef ATKDBG
......@@ -151,4 +145,3 @@ RemoveTailList(list_entry *l)
#define READ_REG(reg,value) (value) = readl((void __iomem *)(&reg))
#endif /* _SLIC_OS_SPECIFIC_H_ */
drivers/staging/sxg/sxghif.h
浏览文件 @ bc36e655
......@@ -277,7 +277,7 @@ typedef struct _SXG_EVENT {
u32 SndUna; // SndUna value
u32 Resid; // receive MDL resid
union {
void * HostHandle; // Receive host handle
void *HostHandle; // Receive host handle
u32 Rsvd1; // TOE NA
struct {
u32 NotUsed;
......@@ -323,7 +323,7 @@ typedef struct _SXG_EVENT {
typedef struct _SXG_EVENT_RING {
SXG_EVENT Ring[EVENT_RING_SIZE];
}SXG_EVENT_RING, *PSXG_EVENT_RING;
} SXG_EVENT_RING, *PSXG_EVENT_RING;
/***************************************************************************
*
......@@ -368,7 +368,6 @@ typedef struct _SXG_EVENT_RING {
&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \
&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
#if DBG
// Horrible kludge to distinguish dumb-nic, slowpath, and
// fastpath traffic. Decrement the HopLimit by one
......@@ -405,7 +404,7 @@ typedef struct _SXG_RING_INFO {
unsigned char Head; // Where we add entries - Note unsigned char:RING_SIZE
unsigned char Tail; // Where we pull off completed entries
ushort Size; // Ring size - Must be multiple of 2
void * Context[SXG_MAX_RING_SIZE]; // Shadow ring
void *Context[SXG_MAX_RING_SIZE]; // Shadow ring
} SXG_RING_INFO, *PSXG_RING_INFO;
#define SXG_INITIALIZE_RING(_ring, _size) { \
......@@ -486,7 +485,7 @@ typedef struct _SXG_CMD {
dma_addr_t Sgl; // Physical address of SGL
union {
struct {
dma64_addr_t FirstSgeAddress;// Address of first SGE
dma64_addr_t FirstSgeAddress; // Address of first SGE
u32 FirstSgeLength; // Length of first SGE
union {
u32 Rsvd1; // TOE NA
......@@ -682,7 +681,7 @@ typedef struct _SXG_RCV_DATA_BUFFER_HDR {
u32 ByteOffset; // See SXG_RESTORE_MDL_OFFSET
unsigned char State; // See SXG_BUFFER state above
unsigned char Status; // Event status (to log PUSH)
struct sk_buff * skb; // Double mapped (nbl and pkt)
struct sk_buff *skb; // Double mapped (nbl and pkt)
} SXG_RCV_DATA_BUFFER_HDR, *PSXG_RCV_DATA_BUFFER_HDR;
// SxgSlowReceive uses the PACKET (skb) contained
......@@ -696,7 +695,7 @@ typedef struct _SXG_RCV_DATA_BUFFER_HDR {
// Receive data descriptor
typedef struct _SXG_RCV_DATA_DESCRIPTOR {
union {
struct sk_buff * VirtualAddress; // Host handle
struct sk_buff *VirtualAddress; // Host handle
u64 ForceTo8Bytes; // Force x86 to 8-byte boundary
};
dma_addr_t PhysicalAddress;
......@@ -711,7 +710,7 @@ typedef struct _SXG_RCV_DESCRIPTOR_BLOCK {
// Receive descriptor block header
typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR {
void * VirtualAddress; // Start of 2k buffer
void *VirtualAddress; // Start of 2k buffer
dma_addr_t PhysicalAddress; // ..and it's physical address
LIST_ENTRY FreeList; // Free queue of descriptor blocks
unsigned char State; // See SXG_BUFFER state above
......@@ -719,7 +718,7 @@ typedef struct _SXG_RCV_DESCRIPTOR_BLOCK_HDR {
// Receive block header
typedef struct _SXG_RCV_BLOCK_HDR {
void * VirtualAddress; // Start of virtual memory
void *VirtualAddress; // Start of virtual memory
dma_addr_t PhysicalAddress; // ..and it's physical address
LIST_ENTRY AllList; // Queue of all SXG_RCV_BLOCKS
} SXG_RCV_BLOCK_HDR, *PSXG_RCV_BLOCK_HDR;
......@@ -748,7 +747,7 @@ typedef struct _SXG_RCV_BLOCK_HDR {
// our SXG_RCV_DATA_BUFFER_HDR structure.
typedef struct _SXG_RCV_NBL_RESERVED {
PSXG_RCV_DATA_BUFFER_HDR RcvDataBufferHdr;
void * Available;
void *Available;
} SXG_RCV_NBL_RESERVED, *PSXG_RCV_NBL_RESERVED;
#define SXG_RCV_NBL_BUFFER_HDR(_NBL) (((PSXG_RCV_NBL_RESERVED)NET_BUFFER_LIST_MINIPORT_RESERVED(_NBL))->RcvDataBufferHdr)
......@@ -760,7 +759,6 @@ typedef struct _SXG_RCV_NBL_RESERVED {
#define SXG_MIN_SGL_BUFFERS 2048 // Minimum amount and when to get more
#define SXG_MAX_SGL_BUFFERS 16384 // Maximum to allocate (note ADAPT:ushort)
// Self identifying structure type
typedef enum _SXG_SGL_TYPE {
SXG_SGL_DUMB, // Dumb NIC SGL
......@@ -803,21 +801,20 @@ typedef enum _SXG_SGL_TYPE {
typedef struct _SXG_X64_SGE {
dma64_addr_t Address; // same as wdm.h
u32 Length; // same as wdm.h
u32 CompilerPad;// The compiler pads to 8-bytes
u32 CompilerPad; // The compiler pads to 8-bytes
u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
} SXG_X64_SGE, *PSXG_X64_SGE;
typedef struct _SCATTER_GATHER_ELEMENT {
dma64_addr_t Address; // same as wdm.h
u32 Length; // same as wdm.h
u32 CompilerPad;// The compiler pads to 8-bytes
u32 CompilerPad; // The compiler pads to 8-bytes
u64 Reserved; // u32 * in wdm.h. Force to 8 bytes
} SCATTER_GATHER_ELEMENT, *PSCATTER_GATHER_ELEMENT;
typedef struct _SCATTER_GATHER_LIST {
u32 NumberOfElements;
u32 * Reserved;
u32 *Reserved;
SCATTER_GATHER_ELEMENT Elements[];
} SCATTER_GATHER_LIST, *PSCATTER_GATHER_LIST;
......@@ -827,19 +824,19 @@ typedef struct _SCATTER_GATHER_LIST {
// we can specify SXG_X64_SGE and define a fixed number of elements
typedef struct _SXG_X64_SGL {
u32 NumberOfElements;
u32 * Reserved;
u32 *Reserved;
SXG_X64_SGE Elements[SXG_SGL_ENTRIES];
} SXG_X64_SGL, *PSXG_X64_SGL;
typedef struct _SXG_SCATTER_GATHER {
SXG_SGL_TYPE Type; // FIRST! Dumb-nic or offload
void * adapter; // Back pointer to adapter
void *adapter; // Back pointer to adapter
LIST_ENTRY FreeList; // Free SXG_SCATTER_GATHER blocks
LIST_ENTRY AllList; // All SXG_SCATTER_GATHER blocks
dma_addr_t PhysicalAddress;// physical address
dma_addr_t PhysicalAddress; // physical address
unsigned char State; // See SXG_BUFFER state above
unsigned char CmdIndex; // Command ring index
struct sk_buff * DumbPacket; // Associated Packet
struct sk_buff *DumbPacket; // Associated Packet
u32 Direction; // For asynchronous completions
u32 CurOffset; // Current SGL offset
u32 SglRef; // SGL reference count
......@@ -856,6 +853,5 @@ typedef struct _SXG_SCATTER_GATHER {
#define SXG_SGL_BUFFER(_SxgSgl) NULL
#define SXG_SGL_BUF_SIZE 0
#else
Stop Compilation;
Stop Compilation;
#endif
drivers/staging/sxg/sxgphycode.h
浏览文件 @ bc36e655
......@@ -53,7 +53,7 @@ static PHY_UCODE PhyUcode[] = {
/* Transceiver-specific MDIO Patches: */
{0xc010, 0x448a}, /* (bit 14) mask out high BER input from the */
/* LOS signal in 1.000A */
/* (mandatory patch for SR code)*/
/* (mandatory patch for SR code) */
{0xc003, 0x0181}, /* (bit 7) enable the CDR inc setting in */
/* 1.C005 (mandatory patch for SR code) */
......
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