sw64: perf: fix the number of supported raw events

Sunway inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I56X48

--------------------------------

According to CORE3B core software interface manual, the performance
counter PC_1 on sw64 supports event index up to 0x3d. Now fix it,
and remove some unused macros from wrperfmon.h.
Signed-off-by: NHe Chuyue <hechuyue@wxiat.com>
Signed-off-by: NGu Zitao <guzitao@wxiat.com>

arch/sw_64/include/asm/wrperfmon.h

@@ -33,10 +33,8 @@
 
 #define PC0_RAW_BASE			0x0
 #define PC1_RAW_BASE			0x100
-#define PC0_MIN				0x0
 #define PC0_MAX				0xF
-#define PC1_MIN				0x0
-#define PC1_MAX				0x37
+#define PC1_MAX				0x3D
 
 #define SW64_PERFCTRL_KM		2
 #define SW64_PERFCTRL_UM		3

arch/sw_64/kernel/perf_event.c

@@ -244,7 +244,7 @@ static const struct sw64_perf_event *core3_map_cache_event(u64 config)
 
 /*
  * r0xx for counter0, r1yy for counter1.
- * According to the datasheet, 00 <= xx <= 0F, 00 <= yy <= 37
+ * According to the datasheet, 00 <= xx <= 0F, 00 <= yy <= 3D
  */
 static bool core3_raw_event_valid(u64 config)
 {