提交 b9a98429 编写于 作者: Y Youling Tang 提交者: openeuler-sync-bot

LoongArch: Add JUMP_VIRT_ADDR macro implementation to avoid using la.abs

LoongArch inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I736HO

--------------------------------

Add JUMP_VIRT_ADDR macro implementation to avoid using la.abs directly.
This is a preparation for subsequent patches.
Signed-off-by: NYouling Tang <tangyouling@loongson.cn>
Change-Id: I4b64da6d5ab46b6bc561b74f39224765f6892758
(cherry picked from commit c066ef2f)
上级 a127549b
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include <asm/asm.h> #include <asm/asm.h>
#include <asm/asmmacro.h> #include <asm/asmmacro.h>
#include <asm/asm-offsets.h> #include <asm/asm-offsets.h>
#include <asm/addrspace.h>
#include <asm/loongarch.h> #include <asm/loongarch.h>
#include <asm/thread_info.h> #include <asm/thread_info.h>
...@@ -36,6 +37,14 @@ ...@@ -36,6 +37,14 @@
cfi_restore \reg \offset \docfi cfi_restore \reg \offset \docfi
.endm .endm
/* Jump to the runtime virtual address. */
.macro JUMP_VIRT_ADDR temp1 temp2
li.d \temp1, CACHE_BASE
pcaddi \temp2, 0
or \temp1, \temp1, \temp2
jirl zero, \temp1, 0xc
.endm
.macro BACKUP_T0T1 .macro BACKUP_T0T1
csrwr t0, EXCEPTION_KS0 csrwr t0, EXCEPTION_KS0
csrwr t1, EXCEPTION_KS1 csrwr t1, EXCEPTION_KS1
......
...@@ -48,11 +48,8 @@ SYM_CODE_START(kernel_entry) # kernel entry point ...@@ -48,11 +48,8 @@ SYM_CODE_START(kernel_entry) # kernel entry point
li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx li.d t0, CSR_DMW1_INIT # CA, PLV0, 0x9000 xxxx xxxx xxxx
csrwr t0, LOONGARCH_CSR_DMWIN1 csrwr t0, LOONGARCH_CSR_DMWIN1
/* We might not get launched at the address the kernel is linked to, JUMP_VIRT_ADDR t0, t1
so we jump there. */
la.abs t0, 0f
jr t0
0:
/* Enable PG */ /* Enable PG */
li.w t0, 0xb0 # PLV=0, IE=0, PG=1 li.w t0, 0xb0 # PLV=0, IE=0, PG=1
csrwr t0, LOONGARCH_CSR_CRMD csrwr t0, LOONGARCH_CSR_CRMD
...@@ -104,9 +101,8 @@ SYM_CODE_START(smpboot_entry) ...@@ -104,9 +101,8 @@ SYM_CODE_START(smpboot_entry)
li.d t0, CSR_DMW1_INIT # CA, PLV0 li.d t0, CSR_DMW1_INIT # CA, PLV0
csrwr t0, LOONGARCH_CSR_DMWIN1 csrwr t0, LOONGARCH_CSR_DMWIN1
la.abs t0, 0f JUMP_VIRT_ADDR t0, t1
jr t0
0:
/* Enable PG */ /* Enable PG */
li.w t0, 0xb0 # PLV=0, IE=0, PG=1 li.w t0, 0xb0 # PLV=0, IE=0, PG=1
csrwr t0, LOONGARCH_CSR_CRMD csrwr t0, LOONGARCH_CSR_CRMD
......
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
.text .text
SYM_FUNC_START(swsusp_arch_save) SYM_FUNC_START(swsusp_arch_save)
la.abs t0, saved_regs la.pcrel t0, saved_regs
PTR_S ra, t0, PT_R1 PTR_S ra, t0, PT_R1
PTR_S sp, t0, PT_R3 PTR_S sp, t0, PT_R3
PTR_S fp, t0, PT_R22 PTR_S fp, t0, PT_R22
......
...@@ -113,9 +113,8 @@ SYM_CODE_START(loongarch_wakeup_start) ...@@ -113,9 +113,8 @@ SYM_CODE_START(loongarch_wakeup_start)
li.d t0, CSR_DMW1_INIT # CA, PLV0 li.d t0, CSR_DMW1_INIT # CA, PLV0
csrwr t0, LOONGARCH_CSR_DMWIN1 csrwr t0, LOONGARCH_CSR_DMWIN1
la.abs t0, 0f JUMP_VIRT_ADDR t0, t1
jirl zero, t0, 0
0:
la.pcrel t0, acpi_saved_sp la.pcrel t0, acpi_saved_sp
ld.d sp, t0, 0 ld.d sp, t0, 0
SETUP_WAKEUP SETUP_WAKEUP
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册