From b2b964f0647c5156038834dd879f90442e33f2a5 Mon Sep 17 00:00:00 2001 From: Divy Le Ray Date: Thu, 12 Mar 2009 21:13:59 +0000 Subject: [PATCH] cxgb3: prefetch buffer access in GRO mode Elmininate a cache miss when accessing the CPL header within the first aggregated buffer. Signed-off-by: Divy Le Ray Signed-off-by: David S. Miller --- drivers/net/cxgb3/sge.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/cxgb3/sge.c b/drivers/net/cxgb3/sge.c index 90f6f82d3bf2..a482429846eb 100644 --- a/drivers/net/cxgb3/sge.c +++ b/drivers/net/cxgb3/sge.c @@ -2029,6 +2029,8 @@ static void lro_add_page(struct adapter *adap, struct sge_qset *qs, pci_unmap_single(adap->pdev, pci_unmap_addr(sd, dma_addr), fl->buf_size, PCI_DMA_FROMDEVICE); + prefetch(&qs->lro_frag_tbl); + rx_frag += nr_frags; rx_frag->page = sd->pg_chunk.page; rx_frag->page_offset = sd->pg_chunk.offset + offset; @@ -2997,6 +2999,7 @@ int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports, V_NEWTIMER(q->rspq.holdoff_tmr)); mod_timer(&q->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD); + return 0; err_unlock: -- GitLab