diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 8031fbc6b69a2867a043ff4e1655497548631e72..50253efecb562d42f077fb7d86a732e993ab6f1f 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -48,7 +48,7 @@
  * R4000-specific cacheops
  */
 #define Create_Dirty_Excl_D		(Cache_D | 0x0c)
-#define Fill				(Cache_I | 0x14)
+#define Fill_I				(Cache_I | 0x14)
 #define Hit_Writeback_I			(Cache_I | Hit_Writeback)
 #define Hit_Writeback_D			(Cache_D | Hit_Writeback)
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 36a3113487393383c1ed7db98855b629cd0f3bba..89b6839140d7586afc9577e7679e49d21cbaeaaf 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1049,7 +1049,7 @@ static inline void rm7k_erratum31(void)
 			"cache\t%1, 0x3000(%0)\n\t"
 			".set pop\n"
 			:
-			: "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
+			: "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
 	}
 }
 
diff --git a/arch/mips/pmcs-msp71xx/msp_setup.c b/arch/mips/pmcs-msp71xx/msp_setup.c
index d1e59cec116e5854131853f142f7b3c8081fbf19..e0f20f487d96abe5c92fd202afd4ffceb318be8d 100644
--- a/arch/mips/pmcs-msp71xx/msp_setup.c
+++ b/arch/mips/pmcs-msp71xx/msp_setup.c
@@ -55,7 +55,7 @@ void msp7120_reset(void)
 
 	for (iptr = (void *)((unsigned int)start & ~(L1_CACHE_BYTES - 1));
 	     iptr < end; iptr += L1_CACHE_BYTES)
-		cache_op(Fill, iptr);
+		cache_op(Fill_I, iptr);
 
 	__asm__ __volatile__ (
 		"startpoint:					\n"