From a3170c1f924ce2565c4e160b9b095e65c03b2dc6 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Wed, 23 Feb 2011 10:08:10 +0000 Subject: [PATCH] x86/PCI: derive pcibios_last_bus from ACPI MCFG On various newer Intel systems the PCI bus(ses) the non-core devices live on aren't getting announced by ACPI except through the bus range covered by mmconfig. At least the i7core-edac driver depends on these devices getting detected. Mauro, could you check whether with this change the Xeon 55xx hack in that driver can go away altogether, and with it the bogus exporting of pcibios_scan_specific_bus()? Signed-off-by: Jan Beulich Cc: Mauro Carvalho Chehab Cc: Aristeu Sergio Signed-off-by: Jesse Barnes --- arch/x86/pci/mmconfig-shared.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index e282886616a0..750c346ef50a 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -606,6 +606,16 @@ static void __init __pci_mmcfg_init(int early) if (list_empty(&pci_mmcfg_list)) return; + if (pcibios_last_bus < 0) { + const struct pci_mmcfg_region *cfg; + + list_for_each_entry(cfg, &pci_mmcfg_list, list) { + if (cfg->segment) + break; + pcibios_last_bus = cfg->end_bus; + } + } + if (pci_mmcfg_arch_init()) pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; else { -- GitLab