From 9b2245e9ece3ed3c65b30a3855419cbfe382145e Mon Sep 17 00:00:00 2001 From: "Chang S. Bae" Date: Thu, 21 Oct 2021 15:55:17 -0700 Subject: [PATCH] x86/msr-index: Add MSRs for XFD mainline inclusion from mainline-v5.16-rc1 commit dae1bd58389615d401a84aedc38fa075ef8f7de6 category: feature bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I590ZC CVE: NA Intel-SIG: commit dae1bd583896 x86/msr-index: Add MSRs for XFD. -------------------------------- XFD introduces two MSRs: - IA32_XFD to enable/disable a feature controlled by XFD - IA32_XFD_ERR to expose to the #NM trap handler which feature was tried to be used for the first time. Both use the same xstate-component bitmap format, used by XCR0. Signed-off-by: Chang S. Bae Signed-off-by: Thomas Gleixner Signed-off-by: Chang S. Bae Signed-off-by: Borislav Petkov Link: https://lkml.kernel.org/r/20211021225527.10184-14-chang.seok.bae@intel.com Signed-off-by: Lin Wang --- arch/x86/include/asm/msr-index.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 2f0ca77d24bc..b93228bb1ca4 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -644,6 +644,8 @@ #define MSR_IA32_BNDCFGS_RSVD 0x00000ffc +#define MSR_IA32_XFD 0x000001c4 +#define MSR_IA32_XFD_ERR 0x000001c5 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_APICBASE 0x0000001b -- GitLab