diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f788a39a1df152c80f154d4d5120fdae882fc737..914071393d1c1aaadf2e123db9e26a3f23cca8c9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -222,6 +222,7 @@ static void dcn20_dsc_pg_control(
 {
 	uint32_t power_gate = power_on ? 0 : 1;
 	uint32_t pwr_status = power_on ? 0 : 2;
+	uint32_t org_ip_request_cntl = 0;
 
 	if (hws->ctx->dc->debug.disable_dsc_power_gate)
 		return;
@@ -229,6 +230,10 @@ static void dcn20_dsc_pg_control(
 	if (REG(DOMAIN16_PG_CONFIG) == 0)
 		return;
 
+	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
+
 	switch (dsc_inst) {
 	case 0: /* DSC0 */
 		REG_UPDATE(DOMAIN16_PG_CONFIG,
@@ -282,6 +287,9 @@ static void dcn20_dsc_pg_control(
 		BREAK_TO_DEBUGGER();
 		break;
 	}
+
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 }
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index f2c2cbf4114b909658a1fda8f4fc9c756e19f58b..d726f36c5e38cf41322e37d283a4004099211173 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -724,9 +724,6 @@ static const struct dc_debug_options debug_defaults_diags = {
 		.disable_pplib_wm_range = true,
 		.disable_stutter = true,
 		.scl_reset_length10 = true,
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-		.disable_dsc_power_gate = true,
-#endif
 };
 
 void dcn20_dpp_destroy(struct dpp **dpp)