mei: expose hardware power gating state to mei layer
Since the runtime pm and the internal power gating cannot be in complete sync in regards to I/O operations, we need to expose the device hardware internal power gating state to mei layer 2. We add pg_state handler that translate the hw internal pg state to mei layer 2. We add power gating event variable to keep power track of power gating transitions Signed-off-by: NTomas Winkler <tomas.winkler@intel.com> Signed-off-by: NAlexander Usyskin <alexander.usyskin@intel.com> Reviewed-by: NAlexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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