From 93d9e0453e2bb599e0bcced1b914f9b4010180a1 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Thu, 5 May 2022 14:38:07 -0700 Subject: [PATCH] drm/i915/gvt: Use intel_engine_mask_t for ring mask When i915 adds additional PVC blitter instances (in an upcoming patch), the definition of VECS0 will change from bit(10) to bit(18), causing GVT's R_ALL mask to overflow the u16 storage that's currently used. Let's replace the u16 with an intel_engine_mask_t to ensure we avoid this. Cc: Tvrtko Ursulin Cc: Zhi Wang Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-8-matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 2459213b6c87..efad8552d6e6 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -428,7 +428,7 @@ struct cmd_info { #define R_VECS BIT(VECS0) #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) /* rings that support this cmd: BLT/RCS/VCS/VECS */ - u16 rings; + intel_engine_mask_t rings; /* devices that support this cmd: SNB/IVB/HSW/... */ u16 devices; -- GitLab