!1555 net: hns3: fix setting wrong tx_timeout value issue and synchronizes the...

!1555 net: hns3: fix setting wrong tx_timeout value issue and synchronizes the differences between the kernel and openeuler

Merge Pull Request from: @svishen 
 
This patch fix setting wrong tx_timeout value issue and fix some tc bug

issue:
https://gitee.com/openeuler/kernel/issues/I7OL9R 
 
Link:https://gitee.com/openeuler/kernel/pulls/1555 

Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com> 

drivers/net/ethernet/hisilicon/hns3/hns3_ext.c

@@ -392,13 +392,15 @@ EXPORT_SYMBOL(nic_get_port_num_per_chip);
 
 int nic_set_tx_timeout(struct net_device *ndev, int tx_timeout)
 {
+	int watchdog_timeo = tx_timeout * HZ;
+
 	if (nic_netdev_match_check(ndev))
 		return -ENODEV;
 
-	if (tx_timeout <= 0)
+	if (watchdog_timeo <= 0 || watchdog_timeo > HNS3_MAX_TX_TIMEOUT)
 		return -EINVAL;
 
-	ndev->watchdog_timeo = tx_timeout;
+	ndev->watchdog_timeo = watchdog_timeo;
 
 	return 0;
 }

drivers/net/ethernet/hisilicon/hns3/hns3_ext.h

@@ -13,6 +13,7 @@
 #define HNS3_PFC_STORM_PARA_ENABLE 1
 #define HNS3_PFC_STORM_PARA_PERIOD_MIN 5
 #define HNS3_PFC_STORM_PARA_PERIOD_MAX 2000
+#define HNS3_MAX_TX_TIMEOUT (10 * 60 * HZ)
 
 #define nic_set_8211_phy_reg nic_set_phy_reg
 #define nic_get_8211_phy_reg nic_get_phy_reg

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c

@@ -52,7 +52,10 @@ static void hclge_tm_info_to_ieee_ets(struct hclge_dev *hdev,
 
 	for (i = 0; i < HNAE3_MAX_TC; i++) {
 		ets->prio_tc[i] = hdev->tm_info.prio_tc[i];
-		ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
+		if (i < hdev->tm_info.num_tc)
+			ets->tc_tx_bw[i] = hdev->tm_info.pg_info[0].tc_dwrr[i];
+		else
+			ets->tc_tx_bw[i] = 0;
 
 		if (hdev->tm_info.tc_info[i].tc_sch_mode ==
 		    HCLGE_SCH_MODE_SP)
@@ -123,7 +126,8 @@ static u8 hclge_ets_tc_changed(struct hclge_dev *hdev, struct ieee_ets *ets,
 }
 
 static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
-				       struct ieee_ets *ets, bool *changed)
+				       struct ieee_ets *ets, bool *changed,
+				       u8 tc_num)
 {
 	bool has_ets_tc = false;
 	u32 total_ets_bw = 0;
@@ -137,6 +141,13 @@ static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
 				*changed = true;
 			break;
 		case IEEE_8021QAZ_TSA_ETS:
+			if (i >= tc_num) {
+				dev_err(&hdev->pdev->dev,
+					"tc%u is disabled, cannot set ets bw\n",
+					i);
+				return -EINVAL;
+			}
+
 			/* The hardware will switch to sp mode if bandwidth is
 			 * 0, so limit ets bandwidth must be greater than 0.
 			 */
@@ -176,7 +187,7 @@ static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
 	if (ret)
 		return ret;
 
-	ret = hclge_ets_sch_mode_validate(hdev, ets, changed);
+	ret = hclge_ets_sch_mode_validate(hdev, ets, changed, tc_num);
 	if (ret)
 		return ret;
 

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

@@ -708,8 +708,7 @@ static int hclge_dbg_dump_tc(struct hclge_dev *hdev, char *buf, int len)
 	for (i = 0; i < HNAE3_MAX_TC; i++) {
 		sch_mode_str = ets_weight->tc_weight[i] ? "dwrr" : "sp";
 		pos += scnprintf(buf + pos, len - pos, "%u     %4s    %3u\n",
-				 i, sch_mode_str,
-				 hdev->tm_info.pg_info[0].tc_dwrr[i]);
+				 i, sch_mode_str, ets_weight->tc_weight[i]);
 	}
 
 	return 0;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c

@@ -785,6 +785,7 @@ static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
 static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
 {
 #define BW_PERCENT	100
+#define DEFAULT_BW_WEIGHT	1
 
 	u8 i;
 
@@ -806,7 +807,7 @@ static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
 		for (k = 0; k < hdev->tm_info.num_tc; k++)
 			hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;
 		for (; k < HNAE3_MAX_TC; k++)
-			hdev->tm_info.pg_info[i].tc_dwrr[k] = 0;
+			hdev->tm_info.pg_info[i].tc_dwrr[k] = DEFAULT_BW_WEIGHT;
 	}
 }