Blackfin arch: Add Workaround for ANOMALY 05000257

Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NBryan Wu <bryan.wu@analog.com>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

arch/blackfin/lib/ins.S

@@ -29,6 +29,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/blackfin.h>
 
 .align 2
 
@@ -40,10 +41,13 @@ ENTRY(_insl)
 	SSYNC;
 	LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
 .Llong_loop_s:  R0 = [P0];
-.Llong_loop_e: [P1++] = R0;
+		[P1++] = R0;
+		NOP;
+.Llong_loop_e: 	NOP;
 	sti R3;
 	RTS;
 
+
 ENTRY(_insw)
 	P0 = R0;	/* P0 = port */
 	cli R3;
@@ -52,7 +56,9 @@ ENTRY(_insw)
 	SSYNC;
 	LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
 .Lword_loop_s:  R0 = W[P0];
-.Lword_loop_e: W[P1++] = R0;
+		W[P1++] = R0;
+		NOP;
+.Lword_loop_e: 	NOP;
 	sti R3;
 	RTS;
 
@@ -64,6 +70,8 @@ ENTRY(_insb)
 	SSYNC;
 	LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
 .Lbyte_loop_s:  R0 = B[P0];
-.Lbyte_loop_e: B[P1++] = R0;
+		B[P1++] = R0;
+		NOP;
+.Lbyte_loop_e:  NOP;
 	sti R3;
 	RTS;

arch/blackfin/mach-common/entry.S

@@ -181,6 +181,12 @@ ENTRY(_ex_single_step)
 
 _return_from_exception:
 	DEBUG_START_HWTRACE
+#ifdef ANOMALY_05000257
+	R7=LC0;
+	LC0=R7;
+	R7=LC1;
+	LC1=R7;
+#endif
 	(R7:6,P5:4) = [sp++];
 	ASTAT = [sp++];
 	sp = retn;