From 8aa2f922ec8508022432a74969920cd3cdc14393 Mon Sep 17 00:00:00 2001 From: Qiuxu Zhuo Date: Sat, 11 Sep 2021 12:11:53 +0800 Subject: [PATCH] Intel: EDAC, i10nm: Add Intel additional Ice-Lake support mainline inclusion from mainline-v5.3-rc1 commit 5c5d3ac2064ae2466c81d40186bcc09b2d5b7892 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I47H3V CVE: NA -------------------------------- commit 5c5d3ac2064ae2466c81d40186bcc09b2d5b7892 upstream. Two new CPU models share the same memory controller architecture with Jacobsville/Tremont, so can use the same i10nm EDAC driver. Add ICX and ICX-D CPU model numbers for EDAC support. Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Signed-off-by: Youquan Song Signed-off-by: Jackie Liu Signed-off-by: Zheng Zengkai Reviewed-by: Xie XiuQi Signed-off-by: Yang Yingliang --- drivers/edac/i10nm_base.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index 87baed8e0807..eb13f07cdaa5 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -124,6 +124,8 @@ static int i10nm_get_all_munits(void) static const struct x86_cpu_id i10nm_cpuids[] = { { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_TREMONT_X, 0, 0 }, + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ICELAKE_X, 0, 0 }, + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ICELAKE_XEON_D, 0, 0 }, { } }; MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids); -- GitLab