提交 7e3297dc 编写于 作者: T Thomas Bogendoerfer 提交者: Ralf Baechle

[MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES

The introduction of a real dma cache invalidate makes it important
to have a correct cache line size, otherwise the kernel will gives
out two memory segment, which might share one cache line. The R4400
Indy/Indigo2 CPU modules are using a second level cache line size
of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for
IP22.
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
上级 1faf7f25
...@@ -1006,7 +1006,7 @@ config BOOT_ELF32 ...@@ -1006,7 +1006,7 @@ config BOOT_ELF32
config MIPS_L1_CACHE_SHIFT config MIPS_L1_CACHE_SHIFT
int int
default "4" if MACH_DECSTATION default "4" if MACH_DECSTATION
default "7" if SGI_IP27 || SGI_IP28 || SNI_RM default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
default "4" if PMC_MSP4200_EVAL default "4" if PMC_MSP4200_EVAL
default "5" default "5"
......
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