From 7b6d4dea959e246ace80e154b6682116ec7d5b82 Mon Sep 17 00:00:00 2001 From: Yicong Yang Date: Sat, 11 Sep 2021 12:10:23 +0800 Subject: [PATCH] PCI: Add 32 GT/s decoding in some macros mainline inclusion from mainline-v5.7-rc1 commit 9cb3985af63555810bb07de50acdf4170771451d category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I47H3V CVE: NA -------------------------------- Link speed 32.0 GT/s is supported in PCIe r5.0. Add this speed to PCIE_SPEED2STR() and PCIE_SPEED2MBS_ENC() to correctly decode it. This is complementary to de76cda215d5 ("PCI: Decode PCIe 32 GT/s link speed"). Link: https://lore.kernel.org/r/1581937984-40353-2-git-send-email-yangyicong@hisilicon.com Signed-off-by: Yicong Yang Signed-off-by: Bjorn Helgaas Signed-off-by: liyouhong Signed-off-by: Zheng Zengkai Reviewed-by: Xiongfeng Wang Reviewed-by: Xie XiuQi Signed-off-by: Yang Yingliang --- drivers/pci/pci.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 76b34efa67d0..456bdc2b8831 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -255,7 +255,8 @@ void pci_disable_bridge_window(struct pci_dev *dev); /* PCIe link information */ #define PCIE_SPEED2STR(speed) \ - ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ + ((speed) == PCIE_SPEED_32_0GT ? "32 GT/s" : \ + (speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ @@ -263,7 +264,8 @@ void pci_disable_bridge_window(struct pci_dev *dev); /* PCIe speed to Mb/s reduced by encoding overhead */ #define PCIE_SPEED2MBS_ENC(speed) \ - ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ + ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ + (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ -- GitLab