From 6b241c739eda4faea1c437751c5e86fe65c21332 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Sat, 16 Feb 2019 20:32:25 +0800 Subject: [PATCH] Revert "PCI: Fix prefetchable range broken in pci_bridge_check_ranges" hulk inclusion category: cleanup bugzilla: NA CVE: NA ---------------------------------------- This reverts commit a04aa3d925a67578b71641db3dbff738423c5db1. Use https://lore.kernel.org/patchwork/patch/1033697/ instead. Signed-off-by: Yang Yingliang Reviewed-by: Xiongfeng Wang Signed-off-by: Yang Yingliang --- drivers/pci/setup-bus.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 294dd6bce98c..79b1824e83b4 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -773,6 +773,20 @@ static void pci_bridge_check_ranges(struct pci_bus *bus) b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; } } + + /* double check if bridge does support 64 bit pref */ + if (b_res[2].flags & IORESOURCE_MEM_64) { + u32 mem_base_hi, tmp; + pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, + &mem_base_hi); + pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, + 0xffffffff); + pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); + if (!tmp) + b_res[2].flags &= ~IORESOURCE_MEM_64; + pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, + mem_base_hi); + } } /* Helper function for sizing routines: find first available -- GitLab