From 6b1c0854d29adaca7d890ca1c6a16a8e6329a3ca Mon Sep 17 00:00:00 2001 From: Qiuxu Zhuo Date: Fri, 13 Jan 2023 11:28:00 +0800 Subject: [PATCH] EDAC/i10nm: Add Intel Emerald Rapids server support mainline inclusion from mainline-v6.3-rc1 commit e4b2bc6616e21f4a7ce4e7452f716e3db8fe66b6 category: feature bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I7DZRN CVE: NA Intel-SIG: commit e4b2bc6616e2 EDAC/i10nm: Add Intel Emerald Rapids server support. Backport to decode memory error for Intel Emerald Rapids server. -------------------------------- The Emerald Rapids CPU model uses similar memory controller registers as Sapphire Rapids server. Add Emerald Rapids CPU model number ID for EDAC support. Tested-by: Li Zhang Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Link: https://lore.kernel.org/all/20230113032802.41752-1-qiuxu.zhuo@intel.com [ Youquan Song: amend commit log ] Signed-off-by: Youquan Song --- drivers/edac/i10nm_base.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index 6cb51090a673..3ea90669ea51 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -674,6 +674,7 @@ static const struct x86_cpu_id i10nm_cpuids[] = { X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1), X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1), X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg), + X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(EMERALDRAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg), {} }; MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids); -- GitLab