提交 65364bbe 编写于 作者: S Sasha Neftin 提交者: Tony Nguyen

igc: Remove obsolete DMA coalescing code

DMA coalescing is not applicable for i225 parts. This patch comes to tidy
up the driver code.
Signed-off-by: NSasha Neftin <sasha.neftin@intel.com>
Tested-by: NNaama Meir <naamax.meir@linux.intel.com>
Signed-off-by: NTony Nguyen <anthony.l.nguyen@intel.com>
上级 5a9b7bfb
...@@ -662,9 +662,6 @@ ...@@ -662,9 +662,6 @@
*/ */
#define IGC_TW_SYSTEM_100_MASK 0x0000FF00 #define IGC_TW_SYSTEM_100_MASK 0x0000FF00
#define IGC_TW_SYSTEM_100_SHIFT 8 #define IGC_TW_SYSTEM_100_SHIFT 8
#define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
#define IGC_DMACR_DMACTHR_MASK 0x00FF0000
#define IGC_DMACR_DMACTHR_SHIFT 16
/* Reg val to set scale to 1024 nsec */ /* Reg val to set scale to 1024 nsec */
#define IGC_LTRMINV_SCALE_1024 2 #define IGC_LTRMINV_SCALE_1024 2
/* Reg val to set scale to 32768 nsec */ /* Reg val to set scale to 32768 nsec */
......
...@@ -593,20 +593,11 @@ s32 igc_set_ltr_i225(struct igc_hw *hw, bool link) ...@@ -593,20 +593,11 @@ s32 igc_set_ltr_i225(struct igc_hw *hw, bool link)
size = rd32(IGC_RXPBS) & size = rd32(IGC_RXPBS) &
IGC_RXPBS_SIZE_I225_MASK; IGC_RXPBS_SIZE_I225_MASK;
/* Calculations vary based on DMAC settings. */
if (rd32(IGC_DMACR) & IGC_DMACR_DMAC_EN) {
size -= (rd32(IGC_DMACR) &
IGC_DMACR_DMACTHR_MASK) >>
IGC_DMACR_DMACTHR_SHIFT;
/* Convert size to bits. */
size *= 1024 * 8;
} else {
/* Convert size to bytes, subtract the MTU, and then /* Convert size to bytes, subtract the MTU, and then
* convert the size to bits. * convert the size to bits.
*/ */
size *= 1024; size *= 1024;
size *= 8; size *= 8;
}
if (size < 0) { if (size < 0) {
hw_dbg("Invalid effective Rx buffer size %d\n", hw_dbg("Invalid effective Rx buffer size %d\n",
......
...@@ -292,7 +292,6 @@ ...@@ -292,7 +292,6 @@
/* LTR registers */ /* LTR registers */
#define IGC_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ #define IGC_LTRC 0x01A0 /* Latency Tolerance Reporting Control */
#define IGC_DMACR 0x02508 /* DMA Coalescing Control Register */
#define IGC_LTRMINV 0x5BB0 /* LTR Minimum Value */ #define IGC_LTRMINV 0x5BB0 /* LTR Minimum Value */
#define IGC_LTRMAXV 0x5BB4 /* LTR Maximum Value */ #define IGC_LTRMAXV 0x5BB4 /* LTR Maximum Value */
......
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