From 4e53f57b09fdb49cf0059d3ce789eaa57ec33379 Mon Sep 17 00:00:00 2001 From: Weilong Chen Date: Wed, 1 Sep 2021 11:38:18 +0800 Subject: [PATCH] arm64: Add MIDR encoding for HiSilicon Taishan CPUs ascend inclusion category: feature bugzilla: 46922, https://gitee.com/openeuler/kernel/issues/I41AUQ CVE: NA ------------------------------------- Adding the MIDR encodings for HiSilicon Taishan v200 CPUs, which is used in Kunpeng ARM64 server SoCs. TSV200 is the abbreviation of Taishan v200. There are two variants of TSV200, variant 0 and variant 1. Signed-off-by: Weilong Chen Reviewed-by: Kefeng Wang Reviewed-by: Ding Tianhong Signed-off-by: Yang Yingliang Signed-off-by: Hanjun Guo Reviewed-by: Xie XiuQi Signed-off-by: Cheng Jian --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 6b8546363830..db4a3dd04a70 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -99,6 +99,7 @@ #define NVIDIA_CPU_PART_CARMEL 0x004 #define HISI_CPU_PART_TSV110 0xD01 +#define HISI_CPU_PART_TSV200 0xD02 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) @@ -119,6 +120,7 @@ #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) +#define MIDR_HISI_TSV200 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV200) #ifndef __ASSEMBLY__ -- GitLab