From 4dd8ee5db10c9f287e9c925e3e98f3907bd1890d Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Wed, 15 Jan 2014 10:31:47 +0000 Subject: [PATCH] MIPS: Add CP0 CMGCRBase definitions & accessor The CMGCRBase register is defined by the PRA specification as an optional register which indicates the physical base of the MIPS Coherence Manager Global Control Register block. This patch simply adds a definition for the base address field within the register, along with an accessor function for reading the register. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6356/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mipsregs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 1f067cdade19..dde6a786307a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -671,6 +671,10 @@ /* EntryHI bit definition */ #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) +/* CMGCRBase bit definitions */ +#define MIPS_CMGCRB_BASE 11 +#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1)) + /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ @@ -1025,6 +1029,8 @@ do { \ #define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3) + #define read_c0_config() __read_32bit_c0_register($16, 0) #define read_c0_config1() __read_32bit_c0_register($16, 1) #define read_c0_config2() __read_32bit_c0_register($16, 2) -- GitLab