RDMA/hns: Bugfix for pf capabilities

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

This patch do following things:
1. Correct calcution for cqe, srqwqe, idx bt_pg_sz.
2. Configure qpc_timer, cqc_timer and scc parameters only for CS.
3. Some change of TAB and SPACE to keep code same with v5.3.

Fixes: 7670a0309b56 ("RDMA/hns: Get pf capbilities from NCL_CONFIG")

Feature or Bugfix: Bugfix
Signed-off-by: NSirong Wang <wangsirong@huawei.com>
Signed-off-by: NWeihang Li <liweihang@hisilicon.com>
Reviewed-by: Nliuyixian <liuyixian@huawei.com>
Reviewed-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

@@ -1853,7 +1853,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev)
 	caps->pbl_ba_pg_sz	= HNS_ROCE_BA_PG_SZ_SUPPORTED_8K;
 	caps->pbl_buf_pg_sz	= 0;
 	caps->pbl_hop_num	= HNS_ROCE_PBL_HOP_NUM;
-	caps->mtt_ba_pg_sz	= 0;
+	caps->mtt_ba_pg_sz	= HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
 	caps->mtt_buf_pg_sz	= 0;
 	caps->mtt_hop_num	= HNS_ROCE_MTT_HOP_NUM;
 	caps->wqe_sq_hop_num	= HNS_ROCE_SQWQE_HOP_NUM;
@@ -1958,8 +1958,8 @@ static void calc_pg_sz(int obj_num, int obj_size, int hop_num, int ctx_bt_num,
 
 static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
 {
-	struct hns_roce_caps *caps = &hr_dev->caps;
 	struct hns_roce_cmq_desc desc[HNS_ROCE_QUERY_PF_CAPS_CMD_NUM];
+	struct hns_roce_caps *caps = &hr_dev->caps;
 	struct hns_roce_query_pf_caps_a *resp_a;
 	struct hns_roce_query_pf_caps_b *resp_b;
 	struct hns_roce_query_pf_caps_c *resp_c;
@@ -1967,8 +1967,8 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
 	struct hns_roce_query_pf_caps_e *resp_e;
 	int ctx_hop_num;
 	int pbl_hop_num;
-	int i;
 	int ret;
+	int i;
 
 	for (i = 0; i < HNS_ROCE_QUERY_PF_CAPS_CMD_NUM; i++) {
 		hns_roce_cmq_setup_basic_desc(&desc[i],
@@ -2103,6 +2103,7 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
 
 	caps->mtt_entry_sz = HNS_ROCE_V2_MTT_ENTRY_SZ;
 	caps->num_mtt_segs = HNS_ROCE_V2_MAX_MTT_SEGS;
+	caps->mtt_ba_pg_sz = HNS_ROCE_BA_PG_SZ_SUPPORTED_256K;
 	caps->num_cqe_segs = HNS_ROCE_V2_MAX_CQE_SEGS;
 	caps->num_srqwqe_segs = HNS_ROCE_V2_MAX_SRQWQE_SEGS;
 	caps->num_idx_segs = HNS_ROCE_V2_MAX_IDX_SEGS;
@@ -2111,9 +2112,6 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
 	caps->srqc_hop_num = ctx_hop_num;
 	caps->cqc_hop_num = ctx_hop_num;
 	caps->mpt_hop_num = ctx_hop_num;
-	caps->scc_ctx_hop_num = ctx_hop_num;
-	caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
-	caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
 	caps->mtt_hop_num = pbl_hop_num;
 	caps->cqe_hop_num = pbl_hop_num;
 	caps->srqwqe_hop_num = pbl_hop_num;
@@ -2129,19 +2127,23 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
 					  V2_QUERY_PF_CAPS_D_RQWQE_HOP_NUM_S);
 
 	calc_pg_sz(caps->num_qps, caps->qpc_entry_sz, caps->qpc_hop_num,
-		   caps->qpc_bt_num, &caps->qpc_buf_pg_sz,
-		   &caps->qpc_ba_pg_sz, HEM_TYPE_QPC);
+		   caps->qpc_bt_num, &caps->qpc_buf_pg_sz, &caps->qpc_ba_pg_sz,
+		   HEM_TYPE_QPC);
 	calc_pg_sz(caps->num_mtpts, caps->mtpt_entry_sz, caps->mpt_hop_num,
-		   caps->mpt_bt_num, &caps->mpt_buf_pg_sz,
-		   &caps->mpt_ba_pg_sz, HEM_TYPE_MTPT);
+		   caps->mpt_bt_num, &caps->mpt_buf_pg_sz, &caps->mpt_ba_pg_sz,
+		   HEM_TYPE_MTPT);
 	calc_pg_sz(caps->num_cqs, caps->cqc_entry_sz, caps->cqc_hop_num,
-		   caps->cqc_bt_num, &caps->cqc_buf_pg_sz,
-		   &caps->cqc_ba_pg_sz, HEM_TYPE_CQC);
+		   caps->cqc_bt_num, &caps->cqc_buf_pg_sz, &caps->cqc_ba_pg_sz,
+		   HEM_TYPE_CQC);
 	calc_pg_sz(caps->num_srqs, caps->srqc_entry_sz, caps->srqc_hop_num,
 		   caps->srqc_bt_num, &caps->srqc_buf_pg_sz,
 		   &caps->srqc_ba_pg_sz, HEM_TYPE_SRQC);
 
 	if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_B) {
+		caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
+		caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;
+		caps->scc_ctx_hop_num = ctx_hop_num;
+
 		calc_pg_sz(caps->num_qps, caps->scc_ctx_entry_sz,
 			   caps->scc_ctx_hop_num, caps->scc_ctx_bt_num,
 			   &caps->scc_ctx_buf_pg_sz,
@@ -2153,15 +2155,13 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev)
 			   &caps->cqc_timer_ba_pg_sz, HEM_TYPE_CQC_TIMER);
 	}
 
-	calc_pg_sz(caps->max_wqes, caps->mtt_entry_sz, caps->mtt_hop_num, 1,
-		   &caps->mtt_buf_pg_sz, &caps->mtt_ba_pg_sz, HEM_TYPE_MTT);
-	calc_pg_sz(caps->max_cqes, caps->cq_entry_sz, caps->cqe_hop_num, 1,
-		   &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
-	calc_pg_sz(caps->max_srq_wrs, caps->mtt_entry_sz, caps->srqwqe_hop_num,
-		   1, &caps->srqwqe_buf_pg_sz, &caps->srqwqe_ba_pg_sz,
-		   HEM_TYPE_SRQWQE);
-	calc_pg_sz(caps->max_srq_wrs, caps->idx_entry_sz, caps->idx_hop_num, 1,
-		   &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
+	calc_pg_sz(caps->num_cqe_segs, caps->mtt_entry_sz, caps->cqe_hop_num,
+		   1, &caps->cqe_buf_pg_sz, &caps->cqe_ba_pg_sz, HEM_TYPE_CQE);
+	calc_pg_sz(caps->num_srqwqe_segs, caps->mtt_entry_sz,
+		   caps->srqwqe_hop_num, 1, &caps->srqwqe_buf_pg_sz,
+		   &caps->srqwqe_ba_pg_sz, HEM_TYPE_SRQWQE);
+	calc_pg_sz(caps->num_idx_segs, caps->idx_entry_sz, caps->idx_hop_num,
+		   1, &caps->idx_buf_pg_sz, &caps->idx_ba_pg_sz, HEM_TYPE_IDX);
 
 	return 0;
 }