!207 [5.10] [bugfix] : merge net-swift txgbe out_of_tree module v1.2.3 to...

!207 [5.10] [bugfix] : merge net-swift  txgbe out_of_tree module v1.2.3 to openEuler/txgbe for some known bugs

Merge Pull Request from: @duanqiangwen 
 
This PR is to merge net-swift linux driver txgbe out_of_tree module v1.2.3 to openEuler/txbge for some known bugfix.

Kernel Issue:
https://gitee.com/openeuler/kernel/issues/I5Y6RT

Bugfix：
1.add cl72_prbs control
2.fix bug of backplane down restart an73
3.fix speed change bug of marvell xaui phy when executing "ethtool -s ethName"
4.fix bug of mac related register configurations in kx4/kx mode
5.adjust input parameters in configure file
6.fix bug of "ethtool -p" function with ocp card
7.fix QinQ TCP/UDP packet traffic bug
8.fix bug of autonegoation between KR board and botong switch chip
9.add support for "ethtool -N xxx ... action"
10.fix bug when in kr mode, core dumping will occassionally happen while os is booting up
11.add support for "ethtool -f xxx" to burn firmware
12.fix flow director udp port match function bug
13.fix bug of "ethtool -f" 
14.fix bug of the case that link down event in kr mode may occasionally cause kernel call trace in kr mode
15.change flow director default mode from perfect mode to signature mode so that queue vectors can be bound to cpus automatically
16.add FEC support in kr mode
17.add support for led and polarity configuration in firmware.
18.add NETDEV_F_HW_CSUM feature support
19.turn on/off led light when execute "ifconfig up/down"
20.fix bug of geneve dst port error setting when enable geneve hw offload
21.fix bug of advertise speed error showing by "ethtool -s"
22.fix bug of vxlan/geneve hw offload feature. 
23.Add support for vxlan/geneve port number setting in hardware register.
24.add support for oem ssid and svid.
25.add inspur oem ssid 0x0075 support for "ethtool -p". Use speed led to blink.
26.add flash unlock when upgrading image  

Net-Swift Official Website:
https://www.net-swift.com
Txgbe Out-of-Tree Linux Driver Source Code:
Click https://www.net-swift.com/p/contact to contact us. 
 
Link:https://gitee.com/openeuler/kernel/pulls/207 
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com> 
Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com> 

drivers/net/ethernet/netswift/Kconfig

@@ -16,6 +16,49 @@ config NET_VENDOR_NETSWIFT
 
 if NET_VENDOR_NETSWIFT
 
-source "drivers/net/ethernet/netswift/txgbe/Kconfig"
+config TXGBE
+	tristate "Netswift PCI-Express 10Gigabit Ethernet support"
+	depends on PCI
+	imply PTP_1588_CLOCK
+	help
+	  This driver supports Netswift 10gigabit ethernet adapters.
+	  For more information on how to identify your adapter, go
+	  to <http://www.net-swift.com>
+
+	  To compile this driver as a module, choose M here. The module
+	  will be called txgbe.
+config TXGBE_HWMON
+	bool "Netswift PCI-Express 10Gigabit adapters HWMON support"
+	default n
+	depends on TXGBE && HWMON && !(TXGBE=y && HWMON=m)
+	help
+	  Say Y if you want to expose thermal sensor data on these devices.
+
+	  If unsure, say N.
+
+config TXGBE_DEBUG_FS
+	bool "Netswift PCI-Express 10Gigabit adapters debugfs support"
+	default n
+	depends on TXGBE
+	help
+	  Say Y if you want to setup debugfs for these devices.
+
+	  If unsure, say N.
+	  
+config TXGBE_POLL_LINK_STATUS
+	bool "Netswift PCI-Express 10Gigabit adapters poll mode support"
+	default n
+	depends on TXGBE
+	help
+	  Say Y if you want to turn these devices to poll mode instead of interrupt-trigged TX/RX.
+
+	  If unsure, say N.
+config TXGBE_SYSFS
+	bool "Netswift PCI-Express 10Gigabit adapters sysfs support"
+	default n
+	depends on TXGBE
+	help
+	  Say Y if you want to setup sysfs for these devices.
 
+	  If unsure, say N.
 endif # NET_VENDOR_NETSWIFT

drivers/net/ethernet/netswift/txgbe/Kconfig

-#
-# Netswift driver configuration
-#
-
-config TXGBE
-	tristate "Netswift 10G Network Interface Card"
-	default n
-	depends on PCI_MSI && NUMA && PCI_IOV && DCB
-	help
-	  This driver supports Netswift 10G Ethernet cards.
-	  To compile this driver as part of the kernel, choose Y here.
-	  If unsure, choose N.
-	  The default is N.

drivers/net/ethernet/netswift/txgbe/Makefile

@@ -9,3 +9,7 @@ obj-$(CONFIG_TXGBE) += txgbe.o
 txgbe-objs := txgbe_main.o txgbe_ethtool.o \
               txgbe_hw.o txgbe_phy.o txgbe_bp.o \
               txgbe_mbx.o txgbe_mtd.o txgbe_param.o txgbe_lib.o txgbe_ptp.o
+
+txgbe-$(CONFIG_TXGBE_HWMON) += txgbe_sysfs.o
+txgbe-$(CONFIG_TXGBE_DEBUG_FS) += txgbe_debugfs.o
+txgbe-$(CONFIG_TXGBE_SYSFS) += txgbe_sysfs.o

drivers/net/ethernet/netswift/txgbe/txgbe.h

@@ -67,6 +67,10 @@
 #define CL72_KRTR_PRBS_MODE_EN 0x2fff			/*deepinsw : 512	default to 256*/
 #endif
 
+#ifndef TXGBE_STATIC_ITR
+#define TXGBE_STATIC_ITR 1		/* static itr configure */
+#endif
+
 #ifndef SFI_SET
 #define SFI_SET 0
 #define SFI_MAIN 24
@@ -95,7 +99,6 @@
 #define KX_POST 16
 #endif
 
-
 #ifndef KX4_TXRX_PIN
 #define KX4_TXRX_PIN 0			/*rx : 0xf  tx : 0xf0 */
 #endif
@@ -118,8 +121,8 @@
 #define KR_CL72_TRAINING 1
 #endif
 
-#ifndef KR_REINITED
-#define KR_REINITED 1
+#ifndef KR_NOREINITED
+#define KR_NOREINITED 0
 #endif
 
 #ifndef KR_AN73_PRESET
@@ -140,17 +143,17 @@
 #define TXGBE_DEFAULT_TX_WORK           DEFAULT_TX_WORK
 #else
 #define TXGBE_DEFAULT_TXD               512
-#define TXGBE_DEFAULT_TX_WORK   256
+#define TXGBE_DEFAULT_TX_WORK           256
 #endif
 #define TXGBE_MAX_TXD                   8192
 #define TXGBE_MIN_TXD                   128
 
 #if (PAGE_SIZE < 8192)
 #define TXGBE_DEFAULT_RXD               512
-#define TXGBE_DEFAULT_RX_WORK   256
+#define TXGBE_DEFAULT_RX_WORK           256
 #else
 #define TXGBE_DEFAULT_RXD               256
-#define TXGBE_DEFAULT_RX_WORK   128
+#define TXGBE_DEFAULT_RX_WORK           128
 #endif
 
 #define TXGBE_MAX_RXD                   8192
@@ -474,6 +477,7 @@ enum txgbe_ring_f_enum {
 
 #define MAX_RX_QUEUES   (TXGBE_MAX_FDIR_INDICES + 1)
 #define MAX_TX_QUEUES   (TXGBE_MAX_FDIR_INDICES + 1)
+#define MAX_XDP_QUEUES  (TXGBE_MAX_FDIR_INDICES + 1)
 
 #define TXGBE_MAX_L2A_QUEUES    4
 #define TXGBE_BAD_L2A_QUEUE     3
@@ -552,6 +556,26 @@ struct txgbe_q_vector {
 	struct txgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
 };
 
+#ifdef CONFIG_TXGBE_HWMON
+
+#define TXGBE_HWMON_TYPE_TEMP           0
+#define TXGBE_HWMON_TYPE_ALARMTHRESH    1
+#define TXGBE_HWMON_TYPE_DALARMTHRESH   2
+
+struct hwmon_attr {
+	struct device_attribute dev_attr;
+	struct txgbe_hw *hw;
+	struct txgbe_thermal_diode_data *sensor;
+	char name[19];
+};
+
+struct hwmon_buff {
+	struct device *device;
+	struct hwmon_attr *hwmon_list;
+	unsigned int n_hwmon;
+};
+#endif /* CONFIG_TXGBE_HWMON */
+
 /*
  * microsecond values for various ITR rates shifted by 2 to fit itr register
  * with the first 3 bits reserved 0
@@ -603,6 +627,13 @@ struct txgbe_mac_addr {
 #define TXGBE_MAC_STATE_MODIFIED        0x2
 #define TXGBE_MAC_STATE_IN_USE          0x4
 
+#ifdef CONFIG_TXGBE_PROCFS
+struct txgbe_therm_proc_data {
+	struct txgbe_hw *hw;
+	struct txgbe_thermal_diode_data *sensor_data;
+};
+#endif
+
 /*
  * Only for array allocations in our adapter struct.
  * we can actually assign 64 queue vectors based on our extended-extended
@@ -718,16 +749,17 @@ struct txgbe_adapter {
 	 */
 	u32 flags;
 	u32 flags2;
-	u32 vf_mode;
-	u32 backplane_an;
-	u32 an73;
-	u32 an37;
-	u32 ffe_main;
-	u32 ffe_pre;
-	u32 ffe_post;
-	u32 ffe_set;
-	u32 backplane_mode;
-	u32 backplane_auto;
+	u8  an73_mode;
+	u8  vf_mode;
+	u8  backplane_an;
+	u8  an73;
+	u8  an37;
+	u16 ffe_main;
+	u16 ffe_pre;
+	u16 ffe_post;
+	u8  ffe_set;
+	u8  backplane_mode;
+	u8  backplane_auto;
 
 	bool cloud_mode;
 
@@ -744,6 +776,10 @@ struct txgbe_adapter {
 	unsigned int num_vmdqs; /* does not include pools assigned to VFs */
 	unsigned int queues_per_pool;
 
+	/* XDP */
+	int num_xdp_queues;
+	struct txgbe_ring *xdp_ring[MAX_XDP_QUEUES];
+
 	/* TX */
 	struct txgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
 
@@ -798,6 +834,9 @@ struct txgbe_adapter {
 
 	struct timer_list service_timer;
 	struct work_struct service_task;
+#ifdef CONFIG_TXGBE_POLL_LINK_STATUS
+	struct timer_list link_check_timer;
+#endif
 	struct hlist_head fdir_filter_list;
 	unsigned long fdir_overflow; /* number of times ATR was backed off */
 	union txgbe_atr_input fdir_mask;
@@ -845,6 +884,23 @@ struct txgbe_adapter {
 	__le16 vxlan_port;
 	__le16 geneve_port;
 
+#ifdef CONFIG_TXGBE_SYSFS
+#ifdef CONFIG_TXGBE_HWMON
+	struct hwmon_buff txgbe_hwmon_buff;
+#endif /* CONFIG_TXGBE_HWMON */
+#else /* CONFIG_TXGBE_SYSFS */
+#ifdef CONFIG_TXGBE_PROCFS
+	struct proc_dir_entry *eth_dir;
+	struct proc_dir_entry *info_dir;
+	u64 old_lsc;
+	struct proc_dir_entry *therm_dir;
+	struct txgbe_therm_proc_data therm_data;
+#endif /* CONFIG_TXGBE_PROCFS */
+#endif /* CONFIG_TXGBE_SYSFS */
+
+#ifdef CONFIG_TXGBE_DEBUG_FS
+	struct dentry *txgbe_dbg_adapter;
+#endif /*CONFIG_TXGBE_DEBUG_FS*/
 	u8 default_up;
 
 	unsigned long fwd_bitmask; /* bitmask indicating in use pools */
@@ -914,6 +970,17 @@ struct txgbe_cb {
 
 /* ESX txgbe CIM IOCTL definition */
 
+#ifdef CONFIG_TXGBE_SYSFS
+void txgbe_sysfs_exit(struct txgbe_adapter *adapter);
+int txgbe_sysfs_init(struct txgbe_adapter *adapter);
+#endif /* CONFIG_TXGBE_SYSFS */
+#ifdef CONFIG_TXGBE_PROCFS
+void txgbe_procfs_exit(struct txgbe_adapter *adapter);
+int txgbe_procfs_init(struct txgbe_adapter *adapter);
+int txgbe_procfs_topdir_init(void);
+void txgbe_procfs_topdir_exit(void);
+#endif /* CONFIG_TXGBE_PROCFS */
+
 extern struct dcbnl_rtnl_ops dcbnl_ops;
 int txgbe_copy_dcb_cfg(struct txgbe_adapter *adapter, int tc_max);
 
@@ -974,6 +1041,37 @@ void txgbe_disable_rx_queue(struct txgbe_adapter *adapter,
 void txgbe_vlan_strip_enable(struct txgbe_adapter *adapter);
 void txgbe_vlan_strip_disable(struct txgbe_adapter *adapter);
 
+#if IS_ENABLED(CONFIG_FCOE)
+void txgbe_configure_fcoe(struct txgbe_adapter *adapter);
+int txgbe_fso(struct txgbe_ring *tx_ring,
+		     struct txgbe_tx_buffer *first,
+		     u8 *hdr_len);
+int txgbe_fcoe_ddp(struct txgbe_adapter *adapter,
+			  union txgbe_rx_desc *rx_desc,
+			  struct sk_buff *skb);
+int txgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
+			      struct scatterlist *sgl, unsigned int sgc);
+int txgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
+				 struct scatterlist *sgl, unsigned int sgc);
+int txgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
+int txgbe_setup_fcoe_ddp_resources(struct txgbe_adapter *adapter);
+void txgbe_free_fcoe_ddp_resources(struct txgbe_adapter *adapter);
+int txgbe_fcoe_enable(struct net_device *netdev);
+int txgbe_fcoe_disable(struct net_device *netdev);
+#if IS_ENABLED(CONFIG_DCB)
+u8 txgbe_fcoe_getapp(struct net_device *netdev);
+u8 txgbe_fcoe_setapp(struct txgbe_adapter *adapter, u8 up);
+#endif /* CONFIG_DCB */
+u8 txgbe_fcoe_get_tc(struct txgbe_adapter *adapter);
+int txgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
+#endif /* CONFIG_FCOE */
+
+#ifdef CONFIG_TXGBE_DEBUG_FS
+void txgbe_dbg_adapter_init(struct txgbe_adapter *adapter);
+void txgbe_dbg_adapter_exit(struct txgbe_adapter *adapter);
+void txgbe_dbg_init(void);
+void txgbe_dbg_exit(void);
+#endif /* CONFIG_TXGBE_DEBUG_FS */
 void txgbe_dump(struct txgbe_adapter *adapter);
 
 static inline struct netdev_queue *txring_txq(const struct txgbe_ring *ring)

drivers/net/ethernet/netswift/txgbe/txgbe_ethtool.c

@@ -212,6 +212,7 @@ int txgbe_get_link_ksettings(struct net_device *netdev,
 
 	/* set the advertised speeds */
 	if (hw->phy.autoneg_advertised) {
+		advertising = 0;
 		if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100_FULL)
 			advertising |= ADVERTISED_100baseT_Full;
 		if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL)
@@ -2194,6 +2195,7 @@ static int txgbe_set_phys_id(struct net_device *netdev,
 {
 	struct txgbe_adapter *adapter = netdev_priv(netdev);
 	struct txgbe_hw *hw = &adapter->hw;
+	u16 value = 0;
 
 	switch (state) {
 	case ETHTOOL_ID_ACTIVE:
@@ -2201,17 +2203,58 @@ static int txgbe_set_phys_id(struct net_device *netdev,
 		return 2;
 
 	case ETHTOOL_ID_ON:
-		TCALL(hw, mac.ops.led_on, TXGBE_LED_LINK_UP);
+		if (hw->oem_ssid == 0x0075 && hw->oem_svid == 0x1bd4) {
+			if (adapter->link_up) {
+				switch (adapter->link_speed) {
+				case TXGBE_LINK_SPEED_10GB_FULL:
+					TCALL(hw, mac.ops.led_on, TXGBE_LED_LINK_10G);
+					break;
+				case TXGBE_LINK_SPEED_1GB_FULL:
+					TCALL(hw, mac.ops.led_on, TXGBE_LED_LINK_1G);
+					break;
+				case TXGBE_LINK_SPEED_100_FULL:
+					TCALL(hw, mac.ops.led_on, TXGBE_LED_LINK_100M);
+					break;
+				default:
+					break;
+				}
+			} else 
+				TCALL(hw, mac.ops.led_on, TXGBE_LED_LINK_10G);
+		} else
+			TCALL(hw, mac.ops.led_on, TXGBE_LED_LINK_UP);
 		break;
 
 	case ETHTOOL_ID_OFF:
-		TCALL(hw, mac.ops.led_off, TXGBE_LED_LINK_UP);
+		if (hw->oem_ssid == 0x0075 && hw->oem_svid == 0x1bd4) {
+			if (adapter->link_up) {
+				switch (adapter->link_speed) {
+				case TXGBE_LINK_SPEED_10GB_FULL:
+					TCALL(hw, mac.ops.led_off, TXGBE_LED_LINK_10G);
+					break;
+				case TXGBE_LINK_SPEED_1GB_FULL:
+					TCALL(hw, mac.ops.led_off, TXGBE_LED_LINK_1G);
+					break;
+				case TXGBE_LINK_SPEED_100_FULL:
+					TCALL(hw, mac.ops.led_off, TXGBE_LED_LINK_100M);
+					break;
+				default:
+					break;
+				}
+			} else 
+				TCALL(hw, mac.ops.led_off, TXGBE_LED_LINK_10G);
+		} else
+			TCALL(hw, mac.ops.led_off, TXGBE_LED_LINK_UP);
 		break;
 
 	case ETHTOOL_ID_INACTIVE:
 		/* Restore LED settings */
 		wr32(&adapter->hw, TXGBE_CFG_LED_CTL,
 				adapter->led_reg);
+		if ((hw->subsystem_device_id & 0xF0) == TXGBE_ID_XAUI) {
+			txgbe_read_mdio(&hw->phy_dev, hw->phy.addr, 31, 0xF021, &value);
+			txgbe_write_mdio(&hw->phy_dev, hw->phy.addr, 31, 0xF021,
+							(value & 0xFFFC) | 0x0);
+		}
 		break;
 	}
 
@@ -3319,16 +3362,21 @@ static int txgbe_set_flash(struct net_device *netdev, struct ethtool_flash *ef)
 	if (ret < 0)
 		return ret;
 
-	if (txgbe_mng_present(&adapter->hw)) {
+	if (ef->region == 0) {
+		ret = txgbe_upgrade_flash(&adapter->hw, ef->region,
+							fw->data, fw->size);
+	} else {
+		if (txgbe_mng_present(&adapter->hw)) {
 		ret = txgbe_upgrade_flash_hostif(&adapter->hw, ef->region,
 						fw->data, fw->size);
-	} else
-		ret = -EOPNOTSUPP;
+		} else
+			ret = -EOPNOTSUPP;
+	}
 
 	release_firmware(fw);
 	if (!ret)
 		dev_info(&netdev->dev,
-			 "loaded firmware %s, reload txgbe driver\n", ef->data);
+			 "loaded firmware %s, reboot to make firmware work\n", ef->data);
 	return ret;
 }
 

drivers/net/ethernet/netswift/txgbe/txgbe_hw.h

@@ -27,6 +27,43 @@
 #define TXGBE_EMC_DIODE3_DATA           0x2A
 #define TXGBE_EMC_DIODE3_THERM_LIMIT    0x30
 
+#define SPI_CLK_DIV                        2
+
+#define SPI_CMD_ERASE_CHIP                 4  // SPI erase chip command
+#define SPI_CMD_ERASE_SECTOR               3  // SPI erase sector command
+#define SPI_CMD_WRITE_DWORD                0  // SPI write a dword command
+#define SPI_CMD_READ_DWORD                 1  // SPI read a dword command
+#define SPI_CMD_USER_CMD                   5  // SPI user command
+
+#define SPI_CLK_CMD_OFFSET                28  // SPI command field offset in Command register
+#define SPI_CLK_DIV_OFFSET                25  // SPI clock divide field offset in Command register
+
+#define SPI_TIME_OUT_VALUE             10000
+#define SPI_SECTOR_SIZE          (4 * 1024)  // FLASH sector size is 64KB
+#define SPI_H_CMD_REG_ADDR           0x10104  // SPI Command register address
+#define SPI_H_DAT_REG_ADDR           0x10108  // SPI Data register address
+#define SPI_H_STA_REG_ADDR           0x1010c  // SPI Status register address
+#define SPI_H_USR_CMD_REG_ADDR       0x10110  // SPI User Command register address
+#define SPI_CMD_CFG1_ADDR            0x10118  // Flash command configuration register 1
+#define MISC_RST_REG_ADDR            0x1000c  // Misc reset register address
+#define MGR_FLASH_RELOAD_REG_ADDR    0x101a0  // MGR reload flash read
+
+#define MAC_ADDR0_WORD0_OFFSET_1G    0x006000c  // MAC Address for LAN0, stored in external FLASH
+#define MAC_ADDR0_WORD1_OFFSET_1G    0x0060014
+#define MAC_ADDR1_WORD0_OFFSET_1G    0x007000c  // MAC Address for LAN1, stored in external FLASH
+#define MAC_ADDR1_WORD1_OFFSET_1G    0x0070014
+/* Product Serial Number, stored in external FLASH last sector */
+#define PRODUCT_SERIAL_NUM_OFFSET_1G    0x00f0000
+
+struct txgbe_hic_read_cab {
+	union txgbe_hic_hdr2 hdr;
+	union {
+		u8 d8[252];
+		u16 d16[126];
+		u32 d32[63];
+	} dbuf;
+};
+
 /**
  * Packet Type decoding
  **/
@@ -238,6 +275,9 @@ s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw);
 s32 txgbe_validate_eeprom_checksum(struct txgbe_hw *hw,
 					    u16 *checksum_val);
 s32 txgbe_update_flash(struct txgbe_hw *hw);
+int txgbe_upgrade_flash(struct txgbe_hw *hw, u32 region,
+								const u8 *data, u32 size);
+
 s32 txgbe_write_ee_hostif_buffer(struct txgbe_hw *hw,
 				u16 offset, u16 words, u16 *data);
 s32 txgbe_write_ee_hostif(struct txgbe_hw *hw, u16 offset,
@@ -250,9 +290,13 @@ void txgbe_wr32_epcs(struct txgbe_hw *hw, u32 addr, u32 data);
 void txgbe_wr32_ephy(struct txgbe_hw *hw, u32 addr, u32 data);
 u32 rd32_ephy(struct txgbe_hw *hw, u32 addr);
 
+u32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr);
 s32 txgbe_upgrade_flash_hostif(struct txgbe_hw *hw,  u32 region,
 				const u8 *data, u32 size);
 
+s32 txgbe_close_notify(struct txgbe_hw *hw);
+s32 txgbe_open_notify(struct txgbe_hw *hw);
+
 s32 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg);
 s32 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg);
 

drivers/net/ethernet/netswift/txgbe/txgbe_lib.c

@@ -472,6 +472,7 @@ static void txgbe_set_num_queues(struct txgbe_adapter *adapter)
 	adapter->num_rx_queues = 1;
 	adapter->num_tx_queues = 1;
 	adapter->queues_per_pool = 1;
+	adapter->num_xdp_queues = 0;
 
 	if (txgbe_set_dcb_vmdq_queues(adapter))
 		return;

drivers/net/ethernet/netswift/txgbe/txgbe_mbx.c

@@ -21,7 +21,7 @@
  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  */
 
-
+#include "txgbe_type.h"
 #include "txgbe.h"
 #include "txgbe_mbx.h"
 
@@ -182,6 +182,303 @@ int txgbe_poll_for_ack(struct txgbe_hw *hw, u16 mbx_id)
 	return countdown ? 0 : TXGBE_ERR_MBX;
 }
 
+/**
+ *  txgbe_read_posted_mbx - Wait for message notification and receive message
+ *  @hw: pointer to the HW structure
+ *  @msg: The message buffer
+ *  @size: Length of buffer
+ *  @mbx_id: id of mailbox to write
+ *
+ *  returns SUCCESS if it successfully received a message notification and
+ *  copied it into the receive buffer.
+ **/
+int txgbe_read_posted_mbx(struct txgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)
+{
+	struct txgbe_mbx_info *mbx = &hw->mbx;
+	int err = TXGBE_ERR_MBX;
+
+	if (!mbx->ops.read)
+		goto out;
+
+	err = txgbe_poll_for_msg(hw, mbx_id);
+
+	/* if ack received read message, otherwise we timed out */
+	if (!err)
+		err = TCALL(hw, mbx.ops.read, msg, size, mbx_id);
+out:
+	return err;
+}
+
+/**
+ *  txgbe_write_posted_mbx - Write a message to the mailbox, wait for ack
+ *  @hw: pointer to the HW structure
+ *  @msg: The message buffer
+ *  @size: Length of buffer
+ *  @mbx_id: id of mailbox to write
+ *
+ *  returns SUCCESS if it successfully copied message into the buffer and
+ *  received an ack to that message within delay * timeout period
+ **/
+int txgbe_write_posted_mbx(struct txgbe_hw *hw, u32 *msg, u16 size,
+			   u16 mbx_id)
+{
+	struct txgbe_mbx_info *mbx = &hw->mbx;
+	int err;
+
+	/* exit if either we can't write or there isn't a defined timeout */
+	if (!mbx->timeout)
+		return TXGBE_ERR_MBX;
+
+	/* send msg */
+	err = TCALL(hw, mbx.ops.write, msg, size, mbx_id);
+
+	/* if msg sent wait until we receive an ack */
+	if (!err)
+		err = txgbe_poll_for_ack(hw, mbx_id);
+
+	return err;
+}
+
+/**
+ *  txgbe_init_mbx_ops - Initialize MB function pointers
+ *  @hw: pointer to the HW structure
+ *
+ *  Setups up the mailbox read and write message function pointers
+ **/
+void txgbe_init_mbx_ops(struct txgbe_hw *hw)
+{
+	struct txgbe_mbx_info *mbx = &hw->mbx;
+
+	mbx->ops.read_posted = txgbe_read_posted_mbx;
+	mbx->ops.write_posted = txgbe_write_posted_mbx;
+}
+
+/**
+ *  txgbe_read_v2p_mailbox - read v2p mailbox
+ *  @hw: pointer to the HW structure
+ *
+ *  This function is used to read the v2p mailbox without losing the read to
+ *  clear status bits.
+ **/
+u32 txgbe_read_v2p_mailbox(struct txgbe_hw *hw)
+{
+	u32 v2p_mailbox = rd32(hw, TXGBE_VXMAILBOX);
+
+	v2p_mailbox |= hw->mbx.v2p_mailbox;
+	/* read and clear mirrored mailbox flags */
+	v2p_mailbox |= rd32a(hw, TXGBE_VXMBMEM, TXGBE_VXMAILBOX_SIZE);
+	wr32a(hw, TXGBE_VXMBMEM, TXGBE_VXMAILBOX_SIZE, 0);
+	hw->mbx.v2p_mailbox |= v2p_mailbox & TXGBE_VXMAILBOX_R2C_BITS;
+
+	return v2p_mailbox;
+}
+
+/**
+ *  txgbe_check_for_bit_vf - Determine if a status bit was set
+ *  @hw: pointer to the HW structure
+ *  @mask: bitmask for bits to be tested and cleared
+ *
+ *  This function is used to check for the read to clear bits within
+ *  the V2P mailbox.
+ **/
+int txgbe_check_for_bit_vf(struct txgbe_hw *hw, u32 mask)
+{
+	u32 mailbox = txgbe_read_v2p_mailbox(hw);
+
+	hw->mbx.v2p_mailbox &= ~mask;
+
+	return (mailbox & mask ? 0 : TXGBE_ERR_MBX);
+}
+
+/**
+ *  txgbe_check_for_msg_vf - checks to see if the PF has sent mail
+ *  @hw: pointer to the HW structure
+ *  @mbx_id: id of mailbox to check
+ *
+ *  returns SUCCESS if the PF has set the Status bit or else ERR_MBX
+ **/
+int txgbe_check_for_msg_vf(struct txgbe_hw *hw, u16 __always_unused mbx_id)
+{
+	int err = TXGBE_ERR_MBX;
+
+	/* read clear the pf sts bit */
+	if (!txgbe_check_for_bit_vf(hw, TXGBE_VXMAILBOX_PFSTS)) {
+		err = 0;
+		hw->mbx.stats.reqs++;
+	}
+
+	return err;
+}
+
+/**
+ *  txgbe_check_for_ack_vf - checks to see if the PF has ACK'd
+ *  @hw: pointer to the HW structure
+ *  @mbx_id: id of mailbox to check
+ *
+ *  returns SUCCESS if the PF has set the ACK bit or else ERR_MBX
+ **/
+int txgbe_check_for_ack_vf(struct txgbe_hw *hw, u16 __always_unused mbx_id)
+{
+	int err = TXGBE_ERR_MBX;
+
+	/* read clear the pf ack bit */
+	if (!txgbe_check_for_bit_vf(hw, TXGBE_VXMAILBOX_PFACK)) {
+		err = 0;
+		hw->mbx.stats.acks++;
+	}
+
+	return err;
+}
+
+/**
+ *  txgbe_check_for_rst_vf - checks to see if the PF has reset
+ *  @hw: pointer to the HW structure
+ *  @mbx_id: id of mailbox to check
+ *
+ *  returns true if the PF has set the reset done bit or else false
+ **/
+int txgbe_check_for_rst_vf(struct txgbe_hw *hw, u16 __always_unused mbx_id)
+{
+	int err = TXGBE_ERR_MBX;
+
+	if (!txgbe_check_for_bit_vf(hw, (TXGBE_VXMAILBOX_RSTD |
+	    TXGBE_VXMAILBOX_RSTI))) {
+		err = 0;
+		hw->mbx.stats.rsts++;
+	}
+
+	return err;
+}
+
+/**
+ *  txgbe_obtain_mbx_lock_vf - obtain mailbox lock
+ *  @hw: pointer to the HW structure
+ *
+ *  return SUCCESS if we obtained the mailbox lock
+ **/
+int txgbe_obtain_mbx_lock_vf(struct txgbe_hw *hw)
+{
+	int err = TXGBE_ERR_MBX;
+	u32 mailbox;
+
+	/* Take ownership of the buffer */
+	wr32(hw, TXGBE_VXMAILBOX, TXGBE_VXMAILBOX_VFU);
+
+	/* reserve mailbox for vf use */
+	mailbox = txgbe_read_v2p_mailbox(hw);
+	if (mailbox & TXGBE_VXMAILBOX_VFU)
+		err = 0;
+	else
+		ERROR_REPORT2(TXGBE_ERROR_POLLING,
+			   "Failed to obtain mailbox lock for VF");
+
+	return err;
+}
+
+/**
+ *  txgbe_write_mbx_vf - Write a message to the mailbox
+ *  @hw: pointer to the HW structure
+ *  @msg: The message buffer
+ *  @size: Length of buffer
+ *  @mbx_id: id of mailbox to write
+ *
+ *  returns SUCCESS if it successfully copied message into the buffer
+ **/
+int txgbe_write_mbx_vf(struct txgbe_hw *hw, u32 *msg, u16 size,
+			      u16 __always_unused mbx_id)
+{
+	int err;
+	u16 i;
+
+	/* lock the mailbox to prevent pf/vf race condition */
+	err = txgbe_obtain_mbx_lock_vf(hw);
+	if (err)
+		goto out_no_write;
+
+	/* flush msg and acks as we are overwriting the message buffer */
+	txgbe_check_for_msg_vf(hw, 0);
+	txgbe_check_for_ack_vf(hw, 0);
+
+	/* copy the caller specified message to the mailbox memory buffer */
+	for (i = 0; i < size; i++)
+		wr32a(hw, TXGBE_VXMBMEM, i, msg[i]);
+
+	/* update stats */
+	hw->mbx.stats.msgs_tx++;
+
+	/* Drop VFU and interrupt the PF to tell it a message has been sent */
+	wr32(hw, TXGBE_VXMAILBOX, TXGBE_VXMAILBOX_REQ);
+
+out_no_write:
+	return err;
+}
+
+/**
+ *  txgbe_read_mbx_vf - Reads a message from the inbox intended for vf
+ *  @hw: pointer to the HW structure
+ *  @msg: The message buffer
+ *  @size: Length of buffer
+ *  @mbx_id: id of mailbox to read
+ *
+ *  returns SUCCESS if it successfuly read message from buffer
+ **/
+int txgbe_read_mbx_vf(struct txgbe_hw *hw, u32 *msg, u16 size,
+			     u16 __always_unused mbx_id)
+{
+	int err = 0;
+	u16 i;
+
+	/* lock the mailbox to prevent pf/vf race condition */
+	err = txgbe_obtain_mbx_lock_vf(hw);
+	if (err)
+		goto out_no_read;
+
+	/* copy the message from the mailbox memory buffer */
+	for (i = 0; i < size; i++)
+		msg[i] = rd32a(hw, TXGBE_VXMBMEM, i);
+
+	/* Acknowledge receipt and release mailbox, then we're done */
+	wr32(hw, TXGBE_VXMAILBOX, TXGBE_VXMAILBOX_ACK);
+
+	/* update stats */
+	hw->mbx.stats.msgs_rx++;
+
+out_no_read:
+	return err;
+}
+
+/**
+ *  txgbe_init_mbx_params_vf - set initial values for vf mailbox
+ *  @hw: pointer to the HW structure
+ *
+ *  Initializes the hw->mbx struct to correct values for vf mailbox
+ */
+void txgbe_init_mbx_params_vf(struct txgbe_hw *hw)
+{
+	struct txgbe_mbx_info *mbx = &hw->mbx;
+
+	/* start mailbox as timed out and let the reset_hw call set the timeout
+	 * value to begin communications */
+	mbx->timeout = 0;
+	mbx->udelay = TXGBE_VF_MBX_INIT_DELAY;
+
+	mbx->size = TXGBE_VXMAILBOX_SIZE;
+
+	mbx->ops.read = txgbe_read_mbx_vf;
+	mbx->ops.write = txgbe_write_mbx_vf;
+	mbx->ops.read_posted = txgbe_read_posted_mbx;
+	mbx->ops.write_posted = txgbe_write_posted_mbx;
+	mbx->ops.check_for_msg = txgbe_check_for_msg_vf;
+	mbx->ops.check_for_ack = txgbe_check_for_ack_vf;
+	mbx->ops.check_for_rst = txgbe_check_for_rst_vf;
+
+	mbx->stats.msgs_tx = 0;
+	mbx->stats.msgs_rx = 0;
+	mbx->stats.reqs = 0;
+	mbx->stats.acks = 0;
+	mbx->stats.rsts = 0;
+}
+
 int txgbe_check_for_bit_pf(struct txgbe_hw *hw, u32 mask, int index)
 {
 	u32 mbvficr = rd32(hw, TXGBE_MBVFICR(index));

drivers/net/ethernet/netswift/txgbe/txgbe_mtd.c

@@ -773,6 +773,98 @@ MTD_STATUS mtdGetAutonegSpeedDuplexResolution(
 	return MTD_OK;
 }
 
+/****************************************************************************/
+MTD_STATUS mtdIsBaseTUp(
+	IN MTD_DEV_PTR devPtr,
+	IN MTD_U16 port,
+	OUT MTD_U16 *speed,
+	OUT MTD_BOOL *linkUp)
+{
+	MTD_BOOL speedIsForced;
+	MTD_U16 forcedSpeed, cuSpeed, cuLinkStatus;
+
+	*linkUp = MTD_FALSE;
+	*speed = MTD_ADV_NONE;
+
+	/* first check if speed is forced to one of the speeds not requiring AN to train */
+	ATTEMPT(mtdGetForcedSpeed(devPtr, port, &speedIsForced, &forcedSpeed));
+
+	if (speedIsForced) {
+		/* check if the link is up at the speed it's forced to */
+		ATTEMPT(mtdHwGetPhyRegField(devPtr, port, 3, 0x8008, 14, 2, &cuSpeed));
+		ATTEMPT(mtdHwGetPhyRegField(devPtr, port, 3, 0x8008, 10, 1, &cuLinkStatus));
+
+		switch (forcedSpeed) {
+		case MTD_SPEED_10M_HD_AN_DIS:
+		case MTD_SPEED_10M_FD_AN_DIS:
+		/* might want to add checking the duplex to make sure there
+		 * is no duplex mismatch */
+			if (cuSpeed == MTD_CU_SPEED_10_MBPS) {
+				*speed = forcedSpeed;
+			} else {
+				*speed = MTD_SPEED_MISMATCH;
+			}
+			if (cuLinkStatus) {
+				*linkUp = MTD_TRUE;
+			}
+			break;
+
+		case MTD_SPEED_100M_HD_AN_DIS:
+		case MTD_SPEED_100M_FD_AN_DIS:
+		/* might want to add checking the duplex to make sure there
+		 * is no duplex mismatch */
+			if (cuSpeed == MTD_CU_SPEED_100_MBPS) {
+				*speed = forcedSpeed;
+			} else {
+				*speed = MTD_SPEED_MISMATCH;
+			}
+			if (cuLinkStatus) {
+				*linkUp = MTD_TRUE;
+			}
+			break;
+
+		default:
+			return MTD_FAIL;
+			break;
+		}
+	} else {
+		/* must be going through AN */
+		ATTEMPT(mtdGetAutonegSpeedDuplexResolution(devPtr, port, speed));
+
+		if (*speed != MTD_ADV_NONE) {
+			/* check if the link is up at the speed it's AN to */
+			ATTEMPT(mtdHwGetPhyRegField(devPtr, port, 3, 0x8008, 10, 1, &cuLinkStatus));
+
+			switch (*speed) {
+			case MTD_SPEED_10M_HD:
+			case MTD_SPEED_10M_FD:
+			case MTD_SPEED_100M_HD:
+			case MTD_SPEED_100M_FD:
+			case MTD_SPEED_1GIG_HD:
+			case MTD_SPEED_1GIG_FD:
+			case MTD_SPEED_10GIG_FD:
+			case MTD_SPEED_2P5GIG_FD:
+			case MTD_SPEED_5GIG_FD:
+				if (cuLinkStatus) {
+					*linkUp = MTD_TRUE;
+				}
+				break;
+			default:
+				return MTD_FAIL;
+				break;
+			}
+
+		}
+		/* else link is down, and AN is in progress, */
+	}
+
+	if (*speed == MTD_SPEED_MISMATCH) {
+		return MTD_FAIL;
+	} else {
+		return MTD_OK;
+	}
+}
+
 MTD_STATUS mtdSetPauseAdvertisement(
 	IN MTD_DEV_PTR devPtr,
 	IN MTD_U16 port,

drivers/net/ethernet/netswift/txgbe/txgbe_mtd.h

@@ -1109,6 +1109,14 @@ MTD_STATUS mtdGetAutonegSpeedDuplexResolution
 	OUT MTD_U16 *speedResolution
 );
 
+MTD_STATUS mtdIsBaseTUp
+(
+	IN MTD_DEV_PTR devPtr,
+	IN MTD_U16 port,
+	OUT MTD_U16 *speed,
+	OUT MTD_BOOL *linkUp
+);
+
 MTD_STATUS mtdAutonegIsSpeedDuplexResolutionDone
 (
 	IN MTD_DEV_PTR devPtr,

drivers/net/ethernet/netswift/txgbe/txgbe_param.c

@@ -46,6 +46,9 @@
 	module_param_array(X, int, &num_##X, 0); \
 	MODULE_PARM_DESC(X, desc);
 
+TXGBE_PARAM(an73_train_mode, "an73_train_mode to different switch(0 to centc, 1 to other)");
+#define TXGBE_DEFAULT_FFE_AN73_TRAIN_MODE   0
+
 /* ffe_main (KR/KX4/KX/SFI)
  *
  * Valid Range: 0-60
@@ -213,7 +216,9 @@ TXGBE_PARAM(VMDQ,
  *
  * Default Value: 1
  */
-#define DEFAULT_ITR             1
+#define DEFAULT_ITR             (TXGBE_STATIC_ITR == 0) || \
+		(TXGBE_STATIC_ITR == 1) ? TXGBE_STATIC_ITR : (u16)((1000000/TXGBE_STATIC_ITR) << 2)
+
 TXGBE_PARAM(InterruptThrottleRate,
 		 "Maximum interrupts per second, per vector, "
 	    "(0,1,980-500000), default 1");
@@ -477,6 +482,30 @@ void txgbe_check_options(struct txgbe_adapter *adapter)
 		       "Warning: no configuration for board #%d\n", bd);
 		txgbe_notice("Using defaults for all values\n");
 	}
+
+		{ /* an73_mode */
+			u32 an73_mode;
+			static struct txgbe_option opt = {
+				.type = range_option,
+				.name = "an73_train_mode",
+				.err =
+				  "using default of "__MODULE_STRING(TXGBE_DEFAULT_FFE_AN73_TRAIN_MODE),
+				.def = TXGBE_DEFAULT_FFE_AN73_TRAIN_MODE,
+				.arg = { .r = { .min = 0,
+						.max = 1} }
+			};
+
+			if (num_an73_train_mode > bd ) {
+				an73_mode = an73_train_mode[bd];
+				if (an73_mode == OPTION_UNSET)
+					an73_mode = an73_train_mode[bd];
+				txgbe_validate_option(&an73_mode, &opt);
+				adapter->an73_mode = an73_mode;
+			} else {
+				adapter->an73_mode = 0;
+			}
+		}
+
 		{ /* MAIN */
 			u32 ffe_main;
 			static struct txgbe_option opt = {
@@ -760,6 +789,7 @@ void txgbe_check_options(struct txgbe_adapter *adapter)
 		} else if (opt.def == 0) {
 			rss = min_t(int, txgbe_max_rss_indices(adapter),
 				    num_online_cpus());
+			feature[RING_F_FDIR].limit = (u16)rss;
 			feature[RING_F_RSS].limit = rss;
 		}
 		/* Check Interoperability */

drivers/net/ethernet/netswift/txgbe/txgbe_phy.h

@@ -150,6 +150,9 @@ s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
 					       bool *autoneg);
 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw);
 
+s32 txgbe_get_phy_firmware_version(struct txgbe_hw *hw,
+					   u16 *firmware_version);
+
 s32 txgbe_identify_module(struct txgbe_hw *hw);
 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw);
 s32 txgbe_tn_check_overtemp(struct txgbe_hw *hw);

drivers/net/ethernet/netswift/txgbe/txgbe_ptp.c

@@ -670,8 +670,8 @@ static void txgbe_ptp_link_speed_adjust(struct txgbe_adapter *adapter,
 		*incval = TXGBE_INCVAL_100;
 		break;
 	case TXGBE_LINK_SPEED_1GB_FULL:
-		*shift = TXGBE_INCVAL_SHIFT_FPGA;
-		*incval = TXGBE_INCVAL_FPGA;
+		*shift = TXGBE_INCVAL_SHIFT_1GB;
+		*incval = TXGBE_INCVAL_1GB;
 		break;
 	case TXGBE_LINK_SPEED_10GB_FULL:
 	default: /* TXGBE_LINK_SPEED_10GB_FULL */

drivers/net/ethernet/netswift/txgbe/txgbe_type.h

@@ -128,6 +128,8 @@
 #define TXGBE_WOL_SUP  0x4000
 #define TXGBE_WOL_MASK  0x4000
 
+#define TXGBE_DEV_MASK                          0xf0
+
 /* Combined interface*/
 #define TXGBE_ID_SFI_XAUI						0x50
 
@@ -355,6 +357,7 @@
 #define TXGBE_MIS_PWR                   0x10000
 #define TXGBE_MIS_CTL                   0x10004
 #define TXGBE_MIS_PF_SM                 0x10008
+#define TXGBE_MIS_PRB_CTL               0x10010
 #define TXGBE_MIS_ST                    0x10028
 #define TXGBE_MIS_SWSM                  0x1002C
 #define TXGBE_MIS_RST_ST                0x10030
@@ -392,6 +395,8 @@
 #define TXGBE_MIS_RST_ST_RST_INI_SHIFT  8
 #define TXGBE_MIS_RST_ST_RST_TIM        0x000000FFU
 #define TXGBE_MIS_PF_SM_SM              1
+#define TXGBE_MIS_PRB_CTL_LAN0_UP                0x2
+#define TXGBE_MIS_PRB_CTL_LAN1_UP                0x1
 
 /* Sensors for PVT(Process Voltage Temperature) */
 #define TXGBE_TS_CTL                    0x10300
@@ -2262,6 +2267,12 @@ union txgbe_atr_hash_dword {
 #define FW_FLASH_UPGRADE_WRITE_CMD      0xE4
 #define FW_FLASH_UPGRADE_VERIFY_CMD     0xE5
 #define FW_FLASH_UPGRADE_VERIFY_LEN     0x4
+#define FW_DW_OPEN_NOTIFY               0xE9
+#define FW_DW_CLOSE_NOTIFY              0xEA
+
+#define TXGBE_CHECKSUM_CAP_ST_PASS      0x80658383
+#define TXGBE_CHECKSUM_CAP_ST_FAIL      0x70657376
+
 
 /* Host Interface Command Structures */
 struct txgbe_hic_hdr {
@@ -3028,8 +3039,9 @@ struct txgbe_hw {
 #endif
 	MTD_DEV phy_dev;
 	enum txgbe_link_status link_status;
-	u16 subsystem_id;
-	u16 tpid[8];
+	u16 tpid[8];	
+	u16 oem_ssid;
+	u16 oem_svid;
 };
 
 #define TCALL(hw, func, args...) (((hw)->func != NULL) \