From 3e5fe052b0c0f9c3f4e590f15edc56e67195aca1 Mon Sep 17 00:00:00 2001 From: Wei Wang Date: Sat, 11 Sep 2021 12:13:26 +0800 Subject: [PATCH] Intel: perf/x86: Fix variable types for LBR registers mainline inclusion from mainline-v5.9-rc1 commit 3cb9d5464c1ceea86f6225089b2f7965989cf316 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I47H3V CVE: NA -------------------------------- commit 3cb9d5464c1ceea86f6225089b2f7965989cf316 upstream Backport summary: backport to kernel 4.19.57 for ICX perf topdown support The MSR variable type can be 'unsigned int', which uses less memory than the longer 'unsigned long'. Fix 'struct x86_pmu' for that. The lbr_nr won't be a negative number, so make it 'unsigned int' as well. Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Wei Wang Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20200613080958.132489-2-like.xu@linux.intel.com Signed-off-by: Yunying Sun Signed-off-by: Jackie Liu Signed-off-by: Zheng Zengkai Reviewed-by: Wei Li Reviewed-by: Xie XiuQi Signed-off-by: Yang Yingliang --- arch/x86/events/perf_event.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 24ee113959f6..21745fd662d6 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -664,8 +664,8 @@ struct x86_pmu { /* * Intel LBR */ - unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */ - int lbr_nr; /* hardware stack size */ + unsigned int lbr_tos, lbr_from, lbr_to, + lbr_nr; /* LBR base regs and size */ u64 lbr_sel_mask; /* LBR_SELECT valid bits */ const int *lbr_sel_map; /* lbr_select mappings */ bool lbr_double_abort; /* duplicated lbr aborts */ -- GitLab