dt-bindings: iommu: Add Message Based SPI for hisilicon

ascend inclusion
category: feature
bugzilla: NA
CVE: NA

----------------------------------------------------

Add Message Base SPI optional property for hisilicon
Signed-off-by: NZhou Guanghui <zhouguanghui1@huawei.com>
Reviewed-by: NDing Tianhong <dingtianhong@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

@@ -61,6 +61,14 @@ the PCIe specification.
 		      Set for Cavium ThunderX2 silicon that doesn't support
 		      SMMU page1 register space.
 
+- hisilicon,message-based-spi
+                   : Message based SPI is used for Ascend310 silicon. The addr
+                     of GICD_SETSPIR needs to be configured in the CFG_REG of
+                     SMMU.
+
+- iommu-spi-base
+                   : The addr of GICD_SETSPI
+
 ** Example
 
         smmu@2b400000 {