From 3daa41d9185acae664ecaf92ca0f12f3488b0aae Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Wed, 30 Jun 2021 14:08:34 -0700 Subject: [PATCH] perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support mainline inclusion from mainline-v5.15-rc1 commit 2a8e51eae7c83c29795622cfc794cf83436cc05d category: feature feature: SPR PMU uncore support bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO Intel-SIG: commit 2a8e51eae7c8 perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support This commit is backported for SPR PMU uncore support. ------------------------------------- M3 Intel UPI is the interface between the mesh and the Intel UPI link layer. It is responsible for translating between the mesh protocol packets and the flits that are used for transmitting data across the Intel UPI interface. The layout of the control registers for a M3UPI uncore unit is similar to a UPI uncore unit. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Andi Kleen Link: https://lore.kernel.org/r/1625087320-194204-11-git-send-email-kan.liang@linux.intel.com Signed-off-by: Yunying Sun --- arch/x86/events/intel/uncore_snbep.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index fb6fd7542f4c..14fbb1b12d20 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -5557,6 +5557,11 @@ static struct intel_uncore_type spr_uncore_upi = { .name = "upi", }; +static struct intel_uncore_type spr_uncore_m3upi = { + SPR_UNCORE_PCI_COMMON_FORMAT(), + .name = "m3upi", +}; + #define UNCORE_SPR_NUM_UNCORE_TYPES 12 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { @@ -5569,7 +5574,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { &spr_uncore_imc, &spr_uncore_m2m, &spr_uncore_upi, - NULL, + &spr_uncore_m3upi, NULL, NULL, }; -- GitLab