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提交 3c00079b 编写于 作者: R Russell King
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Merge branch 'msm-core' of git://codeaurora.org/quic/kernel/dwalker/linux-msm into devel-stable

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Documentation/arm/00-INDEX
浏览文件 @ 3c00079b
......@@ -6,6 +6,8 @@ Interrupts
- ARM Interrupt subsystem documentation
IXP2000
- Release Notes for Linux on Intel's IXP2000 Network Processor
msm
- MSM specific documentation
Netwinder
- Netwinder specific documentation
Porting
......
Documentation/arm/msm/gpiomux.txt 0 → 100644
浏览文件 @ 3c00079b
This document provides an overview of the msm_gpiomux interface, which
is used to provide gpio pin multiplexing and configuration on mach-msm
targets.
History
=======
The first-generation API for gpio configuration & multiplexing on msm
is the function gpio_tlmm_config(). This function has a few notable
shortcomings, which led to its deprecation and replacement by gpiomux:
The 'disable' parameter: Setting the second parameter to
gpio_tlmm_config to GPIO_CFG_DISABLE tells the peripheral
processor in charge of the subsystem to perform a look-up into a
low-power table and apply the low-power/sleep setting for the pin.
As the msm family evolved this became problematic. Not all pins
have sleep settings, not all peripheral processors will accept requests
to apply said sleep settings, and not all msm targets have their gpio
subsystems managed by a peripheral processor. In order to get consistent
behavior on all targets, drivers are forced to ignore this parameter,
rendering it useless.
The 'direction' flag: for all mux-settings other than raw-gpio (0),
the output-enable bit of a gpio is hard-wired to a known
input (usually VDD or ground). For those settings, the direction flag
is meaningless at best, and deceptive at worst. In addition, using the
direction flag to change output-enable (OE) directly can cause trouble in
gpiolib, which has no visibility into gpio direction changes made
in this way. Direction control in gpio mode should be made through gpiolib.
Key Features of gpiomux
=======================
- A consistent interface across all generations of msm. Drivers can expect
the same results on every target.
- gpiomux plays nicely with gpiolib. Functions that should belong to gpiolib
are left to gpiolib and not duplicated here. gpiomux is written with the
intent that gpio_chips will call gpiomux reference-counting methods
from their request() and free() hooks, providing full integration.
- Tabular configuration. Instead of having to call gpio_tlmm_config
hundreds of times, gpio configuration is placed in a single table.
- Per-gpio sleep. Each gpio is individually reference counted, allowing only
those lines which are in use to be put in high-power states.
- 0 means 'do nothing': all flags are designed so that the default memset-zero
equates to a sensible default of 'no configuration', preventing users
from having to provide hundreds of 'no-op' configs for unused or
unwanted lines.
Usage
=====
To use gpiomux, provide configuration information for relevant gpio lines
in the msm_gpiomux_configs table. Since a 0 equates to "unconfigured",
only those lines to be managed by gpiomux need to be specified. Here
is a completely fictional example:
struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
[12] = {
.active = GPIOMUX_VALID | GPIOMUX_DRV_8MA | GPIOMUX_FUNC_1,
.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
},
[34] = {
.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
},
};
To indicate that a gpio is in use, call msm_gpiomux_get() to increase
its reference count. To decrease the reference count, call msm_gpiomux_put().
The effect of this configuration is as follows:
When the system boots, gpios 12 and 34 will be initialized with their
'suspended' configurations. All other gpios, which were left unconfigured,
will not be touched.
When msm_gpiomux_get() is called on gpio 12 to raise its reference count
above 0, its active configuration will be applied. Since no other gpio
line has a valid active configuration, msm_gpiomux_get() will have no
effect on any other line.
When msm_gpiomux_put() is called on gpio 12 or 34 to drop their reference
count to 0, their suspended configurations will be applied.
Since no other gpio line has a valid suspended configuration, no other
gpio line will be effected by msm_gpiomux_put(). Since gpio 34 has no valid
active configuration, this is effectively a no-op for gpio 34 as well,
with one small caveat, see the section "About Output-Enable Settings".
All of the GPIOMUX_VALID flags may seem like unnecessary overhead, but
they address some important issues. As unused entries (all those
except 12 and 34) are zero-filled, gpiomux needs a way to distinguish
the used fields from the unused. In addition, the all-zero pattern
is a valid configuration! Therefore, gpiomux defines an additional bit
which is used to indicate when a field is used. This has the pleasant
side-effect of allowing calls to msm_gpiomux_write to use '0' to indicate
that a value should not be changed:
msm_gpiomux_write(0, GPIOMUX_VALID, 0);
replaces the active configuration of gpio 0 with an all-zero configuration,
but leaves the suspended configuration as it was.
Static Configurations
=====================
To install a static configuration, which is applied at boot and does
not change after that, install a configuration with a suspended component
but no active component, as in the previous example:
[34] = {
.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
},
The suspended setting is applied during boot, and the lack of any valid
active setting prevents any other setting from being applied at runtime.
If other subsystems attempting to access the line is a concern, one could
*really* anchor the configuration down by calling msm_gpiomux_get on the
line at initialization to move the line into active mode. With the line
held, it will never be re-suspended, and with no valid active configuration,
no new configurations will be applied.
But then, if having other subsystems grabbing for the line is truly a concern,
it should be reserved with gpio_request instead, which carries an implicit
msm_gpiomux_get.
gpiomux and gpiolib
===================
It is expected that msm gpio_chips will call msm_gpiomux_get() and
msm_gpiomux_put() from their request and free hooks, like this fictional
example:
static int request(struct gpio_chip *chip, unsigned offset)
{
return msm_gpiomux_get(chip->base + offset);
}
static void free(struct gpio_chip *chip, unsigned offset)
{
msm_gpiomux_put(chip->base + offset);
}
...somewhere in a gpio_chip declaration...
.request = request,
.free = free,
This provides important functionality:
- It guarantees that a gpio line will have its 'active' config applied
when the line is requested, and will not be suspended while the line
remains requested; and
- It guarantees that gpio-direction settings from gpiolib behave sensibly.
See "About Output-Enable Settings."
This mechanism allows for "auto-request" of gpiomux lines via gpiolib
when it is suitable. Drivers wishing more exact control are, of course,
free to also use msm_gpiomux_set and msm_gpiomux_get.
About Output-Enable Settings
============================
Some msm targets do not have the ability to query the current gpio
configuration setting. This means that changes made to the output-enable
(OE) bit by gpiolib cannot be consistently detected and preserved by gpiomux.
Therefore, when gpiomux applies a configuration setting, any direction
settings which may have been applied by gpiolib are lost and the default
input settings are re-applied.
For this reason, drivers should not assume that gpio direction settings
continue to hold if they free and then re-request a gpio. This seems like
common sense - after all, anybody could have obtained the line in the
meantime - but it needs saying.
This also means that calls to msm_gpiomux_write will reset the OE bit,
which means that if the gpio line is held by a client of gpiolib and
msm_gpiomux_write is called, the direction setting has been lost and
gpiolib's internal state has been broken.
Release gpio lines before reconfiguring them.
arch/arm/mach-msm/Kconfig
浏览文件 @ 3c00079b
......@@ -10,6 +10,8 @@ config ARCH_MSM7X00A
select MSM_SMD
select MSM_SMD_PKG3
select CPU_V6
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_MSM7X30
bool "MSM7x30"
......@@ -18,6 +20,9 @@ config ARCH_MSM7X30
select MSM_VIC
select CPU_V7
select MSM_REMOTE_SPINLOCK_DEKKERS
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_QSD8X50
bool "QSD8X50"
......@@ -26,6 +31,19 @@ config ARCH_QSD8X50
select MSM_VIC
select CPU_V7
select MSM_REMOTE_SPINLOCK_LDREX
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_MSM8X60
bool "MSM8X60"
select ARM_GIC
select CPU_V7
select MSM_V2_TLMM
select MSM_GPIOMUX
select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
&& !MACH_MSM8X60_FFA)
endchoice
config MSM_SOC_REV_A
......@@ -36,6 +54,9 @@ config ARCH_MSM_ARM11
config ARCH_MSM_SCORPION
bool
config HAS_MSM_DEBUG_UART_PHYS
bool
config MSM_VIC
bool
......@@ -74,6 +95,30 @@ config MACH_QSD8X50A_ST1_5
help
Support for the Qualcomm ST1.5.
config MACH_MSM8X60_RUMI3
depends on ARCH_MSM8X60
bool "MSM8x60 RUMI3"
help
Support for the Qualcomm MSM8x60 RUMI3 emulator.
config MACH_MSM8X60_SURF
depends on ARCH_MSM8X60
bool "MSM8x60 SURF"
help
Support for the Qualcomm MSM8x60 SURF eval board.
config MACH_MSM8X60_SIM
depends on ARCH_MSM8X60
bool "MSM8x60 Simulator"
help
Support for the Qualcomm MSM8x60 simulator.
config MACH_MSM8X60_FFA
depends on ARCH_MSM8X60
bool "MSM8x60 FFA"
help
Support for the Qualcomm MSM8x60 FFA eval board.
endmenu
config MSM_DEBUG_UART
......@@ -82,6 +127,7 @@ config MSM_DEBUG_UART
default 2 if MSM_DEBUG_UART2
default 3 if MSM_DEBUG_UART3
if HAS_MSM_DEBUG_UART_PHYS
choice
prompt "Debug UART"
......@@ -99,11 +145,20 @@ choice
config MSM_DEBUG_UART3
bool "UART3"
endchoice
endif
config MSM_SMD_PKG3
bool
config MSM_PROC_COMM
bool
config MSM_SMD
bool
config MSM_GPIOMUX
bool
config MSM_V2_TLMM
bool
endif
arch/arm/mach-msm/Makefile
浏览文件 @ 3c00079b
obj-y += proc_comm.o
obj-y += io.o idle.o timer.o dma.o
obj-y += vreg.o
obj-y += io.o idle.o timer.o
ifndef CONFIG_ARCH_MSM8X60
obj-y += acpuclock-arm11.o
obj-y += clock.o clock-pcom.o
obj-y += gpio.o
obj-y += dma.o
endif
ifdef CONFIG_MSM_VIC
obj-y += irq-vic.o
else
ifndef CONFIG_ARCH_MSM8X60
obj-y += irq.o
endif
endif
obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
obj-$(CONFIG_MSM_PROC_COMM) += clock.o
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
......@@ -19,4 +23,11 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o d
obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
ifndef CONFIG_MSM_V2_TLMM
obj-y += gpio.o
endif
arch/arm/mach-msm/board-msm7x30.c
浏览文件 @ 3c00079b
......@@ -39,27 +39,11 @@
extern struct sys_timer msm_timer;
#ifdef CONFIG_SERIAL_MSM_CONSOLE
static struct msm_gpio uart2_config_data[] = {
{ GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_RFR"},
{ GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_CTS"},
{ GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
{ GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
};
static void msm7x30_init_uart2(void)
{
msm_gpios_request_enable(uart2_config_data,
ARRAY_SIZE(uart2_config_data));
}
#endif
static struct platform_device *devices[] __initdata = {
#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
&msm_device_uart2,
#endif
&msm_device_smd,
};
static void __init msm7x30_init_irq(void)
......@@ -70,10 +54,6 @@ static void __init msm7x30_init_irq(void)
static void __init msm7x30_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
#ifdef CONFIG_SERIAL_MSM_CONSOLE
msm7x30_init_uart2();
#endif
}
static void __init msm7x30_map_io(void)
......
arch/arm/mach-msm/board-msm8x60.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
void __iomem *gic_cpu_base_addr;
unsigned long clk_get_max_axi_khz(void)
{
return 0;
}
static void __init msm8x60_map_io(void)
{
msm_map_msm8x60_io();
}
static void __init msm8x60_init_irq(void)
{
unsigned int i;
gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
gic_cpu_init(0, MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
/* RUMI does not adhere to GIC spec by enabling STIs by default.
* Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
*/
if (!machine_is_msm8x60_sim())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
* as they are configured as level, which does not play nice with
* handle_percpu_irq.
*/
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
set_irq_handler(i, handle_percpu_irq);
}
}
static void __init msm8x60_init(void)
{
}
MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
arch/arm/mach-msm/board-qsd8x50.c
浏览文件 @ 3c00079b
......@@ -35,20 +35,49 @@
extern struct sys_timer msm_timer;
static struct msm_gpio uart3_config_data[] = {
{ GPIO_CFG(86, 1, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
{ GPIO_CFG(87, 1, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156;
/* Leave smc91x resources empty here, as we'll fill them in
* at run-time: they vary from board to board, and the true
* configuration won't be known until boot.
*/
static struct resource smc91x_resources[] __initdata = {
[0] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device *devices[] __initdata = {
&msm_device_uart3,
static struct platform_device smc91x_device __initdata = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static void msm8x50_init_uart3(void)
static int __init msm_init_smc91x(void)
{
msm_gpios_request_enable(uart3_config_data,
ARRAY_SIZE(uart3_config_data));
if (machine_is_qsd8x50_surf()) {
smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
smc91x_resources[1].start =
gpio_to_irq(qsd8x50_surf_smc91x_gpio);
smc91x_resources[1].end =
gpio_to_irq(qsd8x50_surf_smc91x_gpio);
platform_device_register(&smc91x_device);
}
return 0;
}
module_init(msm_init_smc91x);
static struct platform_device *devices[] __initdata = {
&msm_device_uart3,
&msm_device_smd,
};
static void __init qsd8x50_map_io(void)
{
......@@ -64,7 +93,6 @@ static void __init qsd8x50_init_irq(void)
static void __init qsd8x50_init(void)
{
msm8x50_init_uart3();
platform_add_devices(devices, ARRAY_SIZE(devices));
}
......
arch/arm/mach-msm/clock-dummy.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
struct clk *clk_get(struct device *dev, const char *id)
{
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return -ENOENT;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
arch/arm/mach-msm/devices-msm7x30.c
浏览文件 @ 3c00079b
......@@ -51,6 +51,11 @@ struct platform_device msm_device_uart2 = {
.resource = resources_uart2,
};
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
};
struct clk msm_clocks_7x30[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
......
arch/arm/mach-msm/devices-msm8x60-iommu.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/bootmem.h>
#include <mach/msm_iomap-8x60.h>
#include <mach/irqs-8x60.h>
#include <mach/iommu.h>
static struct resource msm_iommu_jpegd_resources[] = {
{
.start = MSM_IOMMU_JPEGD_PHYS,
.end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
.end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
.end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_vpe_resources[] = {
{
.start = MSM_IOMMU_VPE_PHYS,
.end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
.end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_VPE_CB_SC_SECURE_IRQ,
.end = SMMU_VPE_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_mdp0_resources[] = {
{
.start = MSM_IOMMU_MDP0_PHYS,
.end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
.end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_MDP0_CB_SC_SECURE_IRQ,
.end = SMMU_MDP0_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_mdp1_resources[] = {
{
.start = MSM_IOMMU_MDP1_PHYS,
.end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
.end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_MDP1_CB_SC_SECURE_IRQ,
.end = SMMU_MDP1_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_rot_resources[] = {
{
.start = MSM_IOMMU_ROT_PHYS,
.end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
.end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_ROT_CB_SC_SECURE_IRQ,
.end = SMMU_ROT_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_ijpeg_resources[] = {
{
.start = MSM_IOMMU_IJPEG_PHYS,
.end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
.end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
.end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_vfe_resources[] = {
{
.start = MSM_IOMMU_VFE_PHYS,
.end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
.end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_VFE_CB_SC_SECURE_IRQ,
.end = SMMU_VFE_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_vcodec_a_resources[] = {
{
.start = MSM_IOMMU_VCODEC_A_PHYS,
.end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
.end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
.end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_vcodec_b_resources[] = {
{
.start = MSM_IOMMU_VCODEC_B_PHYS,
.end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
.end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
.end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_gfx3d_resources[] = {
{
.start = MSM_IOMMU_GFX3D_PHYS,
.end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
.end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
.end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_gfx2d0_resources[] = {
{
.start = MSM_IOMMU_GFX2D0_PHYS,
.end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
.end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
.end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device msm_root_iommu_dev = {
.name = "msm_iommu",
.id = -1,
};
static struct msm_iommu_dev jpegd_smmu = {
.name = "jpegd",
.clk_rate = -1
};
static struct msm_iommu_dev vpe_smmu = {
.name = "vpe"
};
static struct msm_iommu_dev mdp0_smmu = {
.name = "mdp0"
};
static struct msm_iommu_dev mdp1_smmu = {
.name = "mdp1"
};
static struct msm_iommu_dev rot_smmu = {
.name = "rot"
};
static struct msm_iommu_dev ijpeg_smmu = {
.name = "ijpeg"
};
static struct msm_iommu_dev vfe_smmu = {
.name = "vfe",
.clk_rate = -1
};
static struct msm_iommu_dev vcodec_a_smmu = {
.name = "vcodec_a"
};
static struct msm_iommu_dev vcodec_b_smmu = {
.name = "vcodec_b"
};
static struct msm_iommu_dev gfx3d_smmu = {
.name = "gfx3d",
.clk_rate = 27000000
};
static struct msm_iommu_dev gfx2d0_smmu = {
.name = "gfx2d0",
.clk_rate = 27000000
};
static struct platform_device msm_device_smmu_jpegd = {
.name = "msm_iommu",
.id = 0,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
.resource = msm_iommu_jpegd_resources,
};
static struct platform_device msm_device_smmu_vpe = {
.name = "msm_iommu",
.id = 1,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
.resource = msm_iommu_vpe_resources,
};
static struct platform_device msm_device_smmu_mdp0 = {
.name = "msm_iommu",
.id = 2,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
.resource = msm_iommu_mdp0_resources,
};
static struct platform_device msm_device_smmu_mdp1 = {
.name = "msm_iommu",
.id = 3,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
.resource = msm_iommu_mdp1_resources,
};
static struct platform_device msm_device_smmu_rot = {
.name = "msm_iommu",
.id = 4,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
.resource = msm_iommu_rot_resources,
};
static struct platform_device msm_device_smmu_ijpeg = {
.name = "msm_iommu",
.id = 5,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
.resource = msm_iommu_ijpeg_resources,
};
static struct platform_device msm_device_smmu_vfe = {
.name = "msm_iommu",
.id = 6,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
.resource = msm_iommu_vfe_resources,
};
static struct platform_device msm_device_smmu_vcodec_a = {
.name = "msm_iommu",
.id = 7,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
.resource = msm_iommu_vcodec_a_resources,
};
static struct platform_device msm_device_smmu_vcodec_b = {
.name = "msm_iommu",
.id = 8,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
.resource = msm_iommu_vcodec_b_resources,
};
static struct platform_device msm_device_smmu_gfx3d = {
.name = "msm_iommu",
.id = 9,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
.resource = msm_iommu_gfx3d_resources,
};
static struct platform_device msm_device_smmu_gfx2d0 = {
.name = "msm_iommu",
.id = 10,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
.resource = msm_iommu_gfx2d0_resources,
};
static struct msm_iommu_ctx_dev jpegd_src_ctx = {
.name = "jpegd_src",
.num = 0,
.mids = {0, -1}
};
static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
.name = "jpegd_dst",
.num = 1,
.mids = {1, -1}
};
static struct msm_iommu_ctx_dev vpe_src_ctx = {
.name = "vpe_src",
.num = 0,
.mids = {0, -1}
};
static struct msm_iommu_ctx_dev vpe_dst_ctx = {
.name = "vpe_dst",
.num = 1,
.mids = {1, -1}
};
static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
.name = "mdp_vg1",
.num = 0,
.mids = {0, 2, -1}
};
static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
.name = "mdp_rgb1",
.num = 1,
.mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
};
static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
.name = "mdp_vg2",
.num = 0,
.mids = {0, 2, -1}
};
static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
.name = "mdp_rgb2",
.num = 1,
.mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
};
static struct msm_iommu_ctx_dev rot_src_ctx = {
.name = "rot_src",
.num = 0,
.mids = {0, -1}
};
static struct msm_iommu_ctx_dev rot_dst_ctx = {
.name = "rot_dst",
.num = 1,
.mids = {1, -1}
};
static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
.name = "ijpeg_src",
.num = 0,
.mids = {0, -1}
};
static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
.name = "ijpeg_dst",
.num = 1,
.mids = {1, -1}
};
static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
.name = "vfe_imgwr",
.num = 0,
.mids = {2, 3, 4, 5, 6, 7, 8, -1}
};
static struct msm_iommu_ctx_dev vfe_misc_ctx = {
.name = "vfe_misc",
.num = 1,
.mids = {0, 1, 9, -1}
};
static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
.name = "vcodec_a_stream",
.num = 0,
.mids = {2, 5, -1}
};
static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
.name = "vcodec_a_mm1",
.num = 1,
.mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
};
static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
.name = "vcodec_b_mm2",
.num = 0,
.mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
};
static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
.name = "gfx3d_rbpa",
.num = 0,
.mids = {-1}
};
static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
.name = "gfx3d_cpvgttc",
.num = 1,
.mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
};
static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
.name = "gfx3d_smmu",
.num = 2,
.mids = {8, 9, 10, 11, 12, -1}
};
static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
.name = "gfx2d0_pixv1_smmu",
.num = 0,
.mids = {0, 3, 4, -1}
};
static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
.name = "gfx2d0_texv3_smmu",
.num = 1,
.mids = {1, 6, 7, -1}
};
static struct platform_device msm_device_jpegd_src_ctx = {
.name = "msm_iommu_ctx",
.id = 0,
.dev = {
.parent = &msm_device_smmu_jpegd.dev,
},
};
static struct platform_device msm_device_jpegd_dst_ctx = {
.name = "msm_iommu_ctx",
.id = 1,
.dev = {
.parent = &msm_device_smmu_jpegd.dev,
},
};
static struct platform_device msm_device_vpe_src_ctx = {
.name = "msm_iommu_ctx",
.id = 2,
.dev = {
.parent = &msm_device_smmu_vpe.dev,
},
};
static struct platform_device msm_device_vpe_dst_ctx = {
.name = "msm_iommu_ctx",
.id = 3,
.dev = {
.parent = &msm_device_smmu_vpe.dev,
},
};
static struct platform_device msm_device_mdp_vg1_ctx = {
.name = "msm_iommu_ctx",
.id = 4,
.dev = {
.parent = &msm_device_smmu_mdp0.dev,
},
};
static struct platform_device msm_device_mdp_rgb1_ctx = {
.name = "msm_iommu_ctx",
.id = 5,
.dev = {
.parent = &msm_device_smmu_mdp0.dev,
},
};
static struct platform_device msm_device_mdp_vg2_ctx = {
.name = "msm_iommu_ctx",
.id = 6,
.dev = {
.parent = &msm_device_smmu_mdp1.dev,
},
};
static struct platform_device msm_device_mdp_rgb2_ctx = {
.name = "msm_iommu_ctx",
.id = 7,
.dev = {
.parent = &msm_device_smmu_mdp1.dev,
},
};
static struct platform_device msm_device_rot_src_ctx = {
.name = "msm_iommu_ctx",
.id = 8,
.dev = {
.parent = &msm_device_smmu_rot.dev,
},
};
static struct platform_device msm_device_rot_dst_ctx = {
.name = "msm_iommu_ctx",
.id = 9,
.dev = {
.parent = &msm_device_smmu_rot.dev,
},
};
static struct platform_device msm_device_ijpeg_src_ctx = {
.name = "msm_iommu_ctx",
.id = 10,
.dev = {
.parent = &msm_device_smmu_ijpeg.dev,
},
};
static struct platform_device msm_device_ijpeg_dst_ctx = {
.name = "msm_iommu_ctx",
.id = 11,
.dev = {
.parent = &msm_device_smmu_ijpeg.dev,
},
};
static struct platform_device msm_device_vfe_imgwr_ctx = {
.name = "msm_iommu_ctx",
.id = 12,
.dev = {
.parent = &msm_device_smmu_vfe.dev,
},
};
static struct platform_device msm_device_vfe_misc_ctx = {
.name = "msm_iommu_ctx",
.id = 13,
.dev = {
.parent = &msm_device_smmu_vfe.dev,
},
};
static struct platform_device msm_device_vcodec_a_stream_ctx = {
.name = "msm_iommu_ctx",
.id = 14,
.dev = {
.parent = &msm_device_smmu_vcodec_a.dev,
},
};
static struct platform_device msm_device_vcodec_a_mm1_ctx = {
.name = "msm_iommu_ctx",
.id = 15,
.dev = {
.parent = &msm_device_smmu_vcodec_a.dev,
},
};
static struct platform_device msm_device_vcodec_b_mm2_ctx = {
.name = "msm_iommu_ctx",
.id = 16,
.dev = {
.parent = &msm_device_smmu_vcodec_b.dev,
},
};
static struct platform_device msm_device_gfx3d_rbpa_ctx = {
.name = "msm_iommu_ctx",
.id = 17,
.dev = {
.parent = &msm_device_smmu_gfx3d.dev,
},
};
static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
.name = "msm_iommu_ctx",
.id = 18,
.dev = {
.parent = &msm_device_smmu_gfx3d.dev,
},
};
static struct platform_device msm_device_gfx3d_smmu_ctx = {
.name = "msm_iommu_ctx",
.id = 19,
.dev = {
.parent = &msm_device_smmu_gfx3d.dev,
},
};
static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
.name = "msm_iommu_ctx",
.id = 20,
.dev = {
.parent = &msm_device_smmu_gfx2d0.dev,
},
};
static struct platform_device msm_device_gfx2d0_texv3_ctx = {
.name = "msm_iommu_ctx",
.id = 21,
.dev = {
.parent = &msm_device_smmu_gfx2d0.dev,
},
};
static struct platform_device *msm_iommu_devs[] = {
&msm_device_smmu_jpegd,
&msm_device_smmu_vpe,
&msm_device_smmu_mdp0,
&msm_device_smmu_mdp1,
&msm_device_smmu_rot,
&msm_device_smmu_ijpeg,
&msm_device_smmu_vfe,
&msm_device_smmu_vcodec_a,
&msm_device_smmu_vcodec_b,
&msm_device_smmu_gfx3d,
&msm_device_smmu_gfx2d0,
};
static struct msm_iommu_dev *msm_iommu_data[] = {
&jpegd_smmu,
&vpe_smmu,
&mdp0_smmu,
&mdp1_smmu,
&rot_smmu,
&ijpeg_smmu,
&vfe_smmu,
&vcodec_a_smmu,
&vcodec_b_smmu,
&gfx3d_smmu,
&gfx2d0_smmu,
};
static struct platform_device *msm_iommu_ctx_devs[] = {
&msm_device_jpegd_src_ctx,
&msm_device_jpegd_dst_ctx,
&msm_device_vpe_src_ctx,
&msm_device_vpe_dst_ctx,
&msm_device_mdp_vg1_ctx,
&msm_device_mdp_rgb1_ctx,
&msm_device_mdp_vg2_ctx,
&msm_device_mdp_rgb2_ctx,
&msm_device_rot_src_ctx,
&msm_device_rot_dst_ctx,
&msm_device_ijpeg_src_ctx,
&msm_device_ijpeg_dst_ctx,
&msm_device_vfe_imgwr_ctx,
&msm_device_vfe_misc_ctx,
&msm_device_vcodec_a_stream_ctx,
&msm_device_vcodec_a_mm1_ctx,
&msm_device_vcodec_b_mm2_ctx,
&msm_device_gfx3d_rbpa_ctx,
&msm_device_gfx3d_cpvgttc_ctx,
&msm_device_gfx3d_smmu_ctx,
&msm_device_gfx2d0_pixv1_ctx,
&msm_device_gfx2d0_texv3_ctx,
};
static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
&jpegd_src_ctx,
&jpegd_dst_ctx,
&vpe_src_ctx,
&vpe_dst_ctx,
&mdp_vg1_ctx,
&mdp_rgb1_ctx,
&mdp_vg2_ctx,
&mdp_rgb2_ctx,
&rot_src_ctx,
&rot_dst_ctx,
&ijpeg_src_ctx,
&ijpeg_dst_ctx,
&vfe_imgwr_ctx,
&vfe_misc_ctx,
&vcodec_a_stream_ctx,
&vcodec_a_mm1_ctx,
&vcodec_b_mm2_ctx,
&gfx3d_rbpa_ctx,
&gfx3d_cpvgttc_ctx,
&gfx3d_smmu_ctx,
&gfx2d0_pixv1_ctx,
&gfx2d0_texv3_ctx,
};
static int msm8x60_iommu_init(void)
{
int ret, i;
ret = platform_device_register(&msm_root_iommu_dev);
if (ret != 0) {
pr_err("Failed to register root IOMMU device!\n");
goto failure;
}
for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
ret = platform_device_add_data(msm_iommu_devs[i],
msm_iommu_data[i],
sizeof(struct msm_iommu_dev));
if (ret != 0) {
pr_err("platform_device_add_data failed, "
"i = %d\n", i);
goto failure_unwind;
}
ret = platform_device_register(msm_iommu_devs[i]);
if (ret != 0) {
pr_err("platform_device_register smmu failed, "
"i = %d\n", i);
goto failure_unwind;
}
}
for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
ret = platform_device_add_data(msm_iommu_ctx_devs[i],
msm_iommu_ctx_data[i],
sizeof(*msm_iommu_ctx_devs[i]));
if (ret != 0) {
pr_err("platform_device_add_data smmu failed, "
"i = %d\n", i);
goto failure_unwind2;
}
ret = platform_device_register(msm_iommu_ctx_devs[i]);
if (ret != 0) {
pr_err("platform_device_register ctx failed, "
"i = %d\n", i);
goto failure_unwind2;
}
}
return 0;
failure_unwind2:
while (--i >= 0)
platform_device_unregister(msm_iommu_ctx_devs[i]);
failure_unwind:
while (--i >= 0)
platform_device_unregister(msm_iommu_devs[i]);
platform_device_unregister(&msm_root_iommu_dev);
failure:
return ret;
}
static void msm8x60_iommu_exit(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
platform_device_unregister(msm_iommu_ctx_devs[i]);
for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
platform_device_unregister(msm_iommu_devs[i]);
platform_device_unregister(&msm_root_iommu_dev);
}
subsys_initcall(msm8x60_iommu_init);
module_exit(msm8x60_iommu_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
arch/arm/mach-msm/devices-qsd8x50.c
浏览文件 @ 3c00079b
......@@ -48,6 +48,11 @@ struct platform_device msm_device_uart3 = {
.resource = resources_uart3,
};
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
};
struct clk msm_clocks_8x50[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
......
arch/arm/mach-msm/gpio.c
浏览文件 @ 3c00079b
/* linux/arch/arm/mach-msm/gpio.c
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
......@@ -14,72 +14,363 @@
*
*/
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <mach/gpio.h>
#include "proc_comm.h"
int gpio_tlmm_config(unsigned config, unsigned disable)
{
return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
}
EXPORT_SYMBOL(gpio_tlmm_config);
int msm_gpios_enable(const struct msm_gpio *table, int size)
{
int rc;
int i;
const struct msm_gpio *g;
for (i = 0; i < size; i++) {
g = table + i;
rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE);
if (rc) {
pr_err("gpio_tlmm_config(0x%08x, GPIO_ENABLE)"
" <%s> failed: %d\n",
g->gpio_cfg, g->label ?: "?", rc);
pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
GPIO_DRVSTR(g->gpio_cfg));
goto err;
}
#include "gpio_hw.h"
#include "gpiomux.h"
#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
#define MSM_GPIO_BANK(bank, first, last) \
{ \
.regs = { \
.out = MSM_GPIO_OUT_##bank, \
.in = MSM_GPIO_IN_##bank, \
.int_status = MSM_GPIO_INT_STATUS_##bank, \
.int_clear = MSM_GPIO_INT_CLEAR_##bank, \
.int_en = MSM_GPIO_INT_EN_##bank, \
.int_edge = MSM_GPIO_INT_EDGE_##bank, \
.int_pos = MSM_GPIO_INT_POS_##bank, \
.oe = MSM_GPIO_OE_##bank, \
}, \
.chip = { \
.base = (first), \
.ngpio = (last) - (first) + 1, \
.get = msm_gpio_get, \
.set = msm_gpio_set, \
.direction_input = msm_gpio_direction_input, \
.direction_output = msm_gpio_direction_output, \
.to_irq = msm_gpio_to_irq, \
.request = msm_gpio_request, \
.free = msm_gpio_free, \
} \
}
#define MSM_GPIO_BROKEN_INT_CLEAR 1
struct msm_gpio_regs {
void __iomem *out;
void __iomem *in;
void __iomem *int_status;
void __iomem *int_clear;
void __iomem *int_en;
void __iomem *int_edge;
void __iomem *int_pos;
void __iomem *oe;
};
struct msm_gpio_chip {
spinlock_t lock;
struct gpio_chip chip;
struct msm_gpio_regs regs;
#if MSM_GPIO_BROKEN_INT_CLEAR
unsigned int_status_copy;
#endif
unsigned int both_edge_detect;
unsigned int int_enable[2]; /* 0: awake, 1: sleep */
};
static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
unsigned offset, unsigned on)
{
unsigned mask = BIT(offset);
unsigned val;
val = readl(msm_chip->regs.out);
if (on)
writel(val | mask, msm_chip->regs.out);
else
writel(val & ~mask, msm_chip->regs.out);
return 0;
err:
msm_gpios_disable(table, i);
return rc;
}
EXPORT_SYMBOL(msm_gpios_enable);
void msm_gpios_disable(const struct msm_gpio *table, int size)
{
int rc;
int i;
const struct msm_gpio *g;
for (i = size-1; i >= 0; i--) {
g = table + i;
rc = gpio_tlmm_config(g->gpio_cfg, GPIO_DISABLE);
if (rc) {
pr_err("gpio_tlmm_config(0x%08x, GPIO_DISABLE)"
" <%s> failed: %d\n",
g->gpio_cfg, g->label ?: "?", rc);
pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
GPIO_DRVSTR(g->gpio_cfg));
}
}
static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
{
int loop_limit = 100;
unsigned pol, val, val2, intstat;
do {
val = readl(msm_chip->regs.in);
pol = readl(msm_chip->regs.int_pos);
pol = (pol & ~msm_chip->both_edge_detect) |
(~val & msm_chip->both_edge_detect);
writel(pol, msm_chip->regs.int_pos);
intstat = readl(msm_chip->regs.int_status);
val2 = readl(msm_chip->regs.in);
if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
return;
} while (loop_limit-- > 0);
printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
"failed to reach stable state %x != %x\n", val, val2);
}
static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
unsigned offset)
{
unsigned bit = BIT(offset);
#if MSM_GPIO_BROKEN_INT_CLEAR
/* Save interrupts that already triggered before we loose them. */
/* Any interrupt that triggers between the read of int_status */
/* and the write to int_clear will still be lost though. */
msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
msm_chip->int_status_copy &= ~bit;
#endif
writel(bit, msm_chip->regs.int_clear);
msm_gpio_update_both_edge_detect(msm_chip);
return 0;
}
static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
struct msm_gpio_chip *msm_chip;
unsigned long irq_flags;
msm_chip = container_of(chip, struct msm_gpio_chip, chip);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
return 0;
}
static int
msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
{
struct msm_gpio_chip *msm_chip;
unsigned long irq_flags;
msm_chip = container_of(chip, struct msm_gpio_chip, chip);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
msm_gpio_write(msm_chip, offset, value);
writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
return 0;
}
static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct msm_gpio_chip *msm_chip;
msm_chip = container_of(chip, struct msm_gpio_chip, chip);
return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
}
static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct msm_gpio_chip *msm_chip;
unsigned long irq_flags;
msm_chip = container_of(chip, struct msm_gpio_chip, chip);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
msm_gpio_write(msm_chip, offset, value);
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
}
static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
return MSM_GPIO_TO_INT(chip->base + offset);
}
#ifdef CONFIG_MSM_GPIOMUX
static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
{
return msm_gpiomux_get(chip->base + offset);
}
static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
{
msm_gpiomux_put(chip->base + offset);
}
#else
#define msm_gpio_request NULL
#define msm_gpio_free NULL
#endif
struct msm_gpio_chip msm_gpio_chips[] = {
#if defined(CONFIG_ARCH_MSM7X00A)
MSM_GPIO_BANK(0, 0, 15),
MSM_GPIO_BANK(1, 16, 42),
MSM_GPIO_BANK(2, 43, 67),
MSM_GPIO_BANK(3, 68, 94),
MSM_GPIO_BANK(4, 95, 106),
MSM_GPIO_BANK(5, 107, 121),
#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27)
MSM_GPIO_BANK(0, 0, 15),
MSM_GPIO_BANK(1, 16, 42),
MSM_GPIO_BANK(2, 43, 67),
MSM_GPIO_BANK(3, 68, 94),
MSM_GPIO_BANK(4, 95, 106),
MSM_GPIO_BANK(5, 107, 132),
#elif defined(CONFIG_ARCH_MSM7X30)
MSM_GPIO_BANK(0, 0, 15),
MSM_GPIO_BANK(1, 16, 43),
MSM_GPIO_BANK(2, 44, 67),
MSM_GPIO_BANK(3, 68, 94),
MSM_GPIO_BANK(4, 95, 106),
MSM_GPIO_BANK(5, 107, 133),
MSM_GPIO_BANK(6, 134, 150),
MSM_GPIO_BANK(7, 151, 181),
#elif defined(CONFIG_ARCH_QSD8X50)
MSM_GPIO_BANK(0, 0, 15),
MSM_GPIO_BANK(1, 16, 42),
MSM_GPIO_BANK(2, 43, 67),
MSM_GPIO_BANK(3, 68, 94),
MSM_GPIO_BANK(4, 95, 103),
MSM_GPIO_BANK(5, 104, 121),
MSM_GPIO_BANK(6, 122, 152),
MSM_GPIO_BANK(7, 153, 164),
#endif
};
static void msm_gpio_irq_ack(unsigned int irq)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
msm_gpio_clear_detect_status(msm_chip,
irq - gpio_to_irq(msm_chip->chip.base));
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
}
static void msm_gpio_irq_mask(unsigned int irq)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
/* level triggered interrupts are also latched */
if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
msm_gpio_clear_detect_status(msm_chip, offset);
msm_chip->int_enable[0] &= ~BIT(offset);
writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
}
static void msm_gpio_irq_unmask(unsigned int irq)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
/* level triggered interrupts are also latched */
if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
msm_gpio_clear_detect_status(msm_chip, offset);
msm_chip->int_enable[0] |= BIT(offset);
writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
}
static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
if (on)
msm_chip->int_enable[1] |= BIT(offset);
else
msm_chip->int_enable[1] &= ~BIT(offset);
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
return 0;
}
static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
{
unsigned long irq_flags;
struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
unsigned val, mask = BIT(offset);
spin_lock_irqsave(&msm_chip->lock, irq_flags);
val = readl(msm_chip->regs.int_edge);
if (flow_type & IRQ_TYPE_EDGE_BOTH) {
writel(val | mask, msm_chip->regs.int_edge);
irq_desc[irq].handle_irq = handle_edge_irq;
} else {
writel(val & ~mask, msm_chip->regs.int_edge);
irq_desc[irq].handle_irq = handle_level_irq;
}
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
msm_chip->both_edge_detect |= mask;
msm_gpio_update_both_edge_detect(msm_chip);
} else {
msm_chip->both_edge_detect &= ~mask;
val = readl(msm_chip->regs.int_pos);
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
writel(val | mask, msm_chip->regs.int_pos);
else
writel(val & ~mask, msm_chip->regs.int_pos);
}
spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
return 0;
}
EXPORT_SYMBOL(msm_gpios_disable);
int msm_gpios_request_enable(const struct msm_gpio *table, int size)
static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
int rc = msm_gpios_enable(table, size);
return rc;
int i, j, mask;
unsigned val;
for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
val = readl(msm_chip->regs.int_status);
val &= msm_chip->int_enable[0];
while (val) {
mask = val & -val;
j = fls(mask) - 1;
/* printk("%s %08x %08x bit %d gpio %d irq %d\n",
__func__, v, m, j, msm_chip->chip.start + j,
FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
val &= ~mask;
generic_handle_irq(FIRST_GPIO_IRQ +
msm_chip->chip.base + j);
}
}
desc->chip->ack(irq);
}
EXPORT_SYMBOL(msm_gpios_request_enable);
void msm_gpios_disable_free(const struct msm_gpio *table, int size)
static struct irq_chip msm_gpio_irq_chip = {
.name = "msmgpio",
.ack = msm_gpio_irq_ack,
.mask = msm_gpio_irq_mask,
.unmask = msm_gpio_irq_unmask,
.set_wake = msm_gpio_irq_set_wake,
.set_type = msm_gpio_irq_set_type,
};
static int __init msm_init_gpio(void)
{
msm_gpios_disable(table, size);
int i, j = 0;
for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
if (i - FIRST_GPIO_IRQ >=
msm_gpio_chips[j].chip.base +
msm_gpio_chips[j].chip.ngpio)
j++;
set_irq_chip_data(i, &msm_gpio_chips[j]);
set_irq_chip(i, &msm_gpio_irq_chip);
set_irq_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID);
}
for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
spin_lock_init(&msm_gpio_chips[i].lock);
writel(0, msm_gpio_chips[i].regs.int_en);
gpiochip_add(&msm_gpio_chips[i].chip);
}
set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
set_irq_wake(INT_GPIO_GROUP1, 1);
set_irq_wake(INT_GPIO_GROUP2, 2);
return 0;
}
EXPORT_SYMBOL(msm_gpios_disable_free);
postcore_initcall(msm_init_gpio);
arch/arm/mach-msm/gpio_hw.h 0 → 100644
浏览文件 @ 3c00079b
/* arch/arm/mach-msm/gpio_hw.h
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
#include <mach/msm_iomap.h>
/* see 80-VA736-2 Rev C pp 695-751
**
** These are actually the *shadow* gpio registers, since the
** real ones (which allow full access) are only available to the
** ARM9 side of the world.
**
** Since the _BASE need to be page-aligned when we're mapping them
** to virtual addresses, adjust for the additional offset in these
** macros.
*/
#if defined(CONFIG_ARCH_MSM7X30)
#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
#else
#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
#endif
#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
defined(CONFIG_ARCH_MSM7X27)
/* output value */
#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */
/* same pin map as above, output enable */
#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
/* same pin map as above, input read */
#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
/* same pin map as above, 1=edge 0=level interrup */
#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
/* same pin map as above, 1=positive 0=negative */
#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
/* same pin map as above, interrupt enable */
#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
/* same pin map as above, write 1 to clear interrupt */
#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
/* same pin map as above, 1=interrupt pending */
#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
#endif
#if defined(CONFIG_ARCH_QSD8X50)
/* output value */
#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */
#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */
#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */
#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */
/* same pin map as above, output enable */
#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20)
#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24)
#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28)
#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C)
#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30)
#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34)
#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38)
/* same pin map as above, input read */
#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50)
#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54)
#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58)
#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C)
#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60)
#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64)
#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68)
/* same pin map as above, 1=edge 0=level interrup */
#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70)
#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74)
#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78)
#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C)
#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80)
#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84)
#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88)
/* same pin map as above, 1=positive 0=negative */
#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90)
#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94)
#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98)
#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C)
#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0)
#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4)
#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8)
/* same pin map as above, interrupt enable */
#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0)
#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4)
#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8)
#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC)
#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0)
#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4)
#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8)
/* same pin map as above, write 1 to clear interrupt */
#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0)
#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4)
#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8)
#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC)
#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0)
#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4)
#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8)
/* same pin map as above, 1=interrupt pending */
#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0)
#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4)
#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8)
#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC)
#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100)
#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104)
#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108)
#endif
#if defined(CONFIG_ARCH_MSM7X30)
/* output value */
#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
/* same pin map as above, output enable */
#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218)
/* same pin map as above, input read */
#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
/* same pin map as above, 1=edge 0=level interrup */
#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
/* same pin map as above, 1=positive 0=negative */
#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
/* same pin map as above, interrupt enable */
#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
/* same pin map as above, write 1 to clear interrupt */
#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
/* same pin map as above, 1=interrupt pending */
#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
#endif
#endif
arch/arm/mach-msm/gpiomux-7x30.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include "gpiomux.h"
struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
#ifdef CONFIG_SERIAL_MSM_CONSOLE
[49] = { /* UART2 RFR */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
},
[50] = { /* UART2 CTS */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
},
[51] = { /* UART2 RX */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
},
[52] = { /* UART2 TX */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_2 | GPIOMUX_VALID,
},
#endif
};
arch/arm/mach-msm/gpiomux-8x50.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include "gpiomux.h"
struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
[86] = { /* UART3 RX */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_1 | GPIOMUX_VALID,
},
[87] = { /* UART3 TX */
.suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
GPIOMUX_FUNC_1 | GPIOMUX_VALID,
},
};
arch/arm/mach-msm/gpiomux-8x60.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include "gpiomux.h"
struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
arch/arm/mach-msm/gpiomux-v1.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/kernel.h>
#include "gpiomux.h"
#include "proc_comm.h"
void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
{
unsigned tlmm_config = (val & ~GPIOMUX_CTL_MASK) |
((gpio & 0x3ff) << 4);
unsigned tlmm_disable = 0;
int rc;
rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
&tlmm_config, &tlmm_disable);
if (rc)
pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
__func__, rc, tlmm_config, tlmm_disable);
}
arch/arm/mach-msm/gpiomux-v1.h 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
#define __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
#if defined(CONFIG_ARCH_MSM7X30)
#define GPIOMUX_NGPIOS 182
#elif defined(CONFIG_ARCH_QSD8X50)
#define GPIOMUX_NGPIOS 165
#else
#define GPIOMUX_NGPIOS 133
#endif
typedef u32 gpiomux_config_t;
enum {
GPIOMUX_DRV_2MA = 0UL << 17,
GPIOMUX_DRV_4MA = 1UL << 17,
GPIOMUX_DRV_6MA = 2UL << 17,
GPIOMUX_DRV_8MA = 3UL << 17,
GPIOMUX_DRV_10MA = 4UL << 17,
GPIOMUX_DRV_12MA = 5UL << 17,
GPIOMUX_DRV_14MA = 6UL << 17,
GPIOMUX_DRV_16MA = 7UL << 17,
};
enum {
GPIOMUX_FUNC_GPIO = 0UL,
GPIOMUX_FUNC_1 = 1UL,
GPIOMUX_FUNC_2 = 2UL,
GPIOMUX_FUNC_3 = 3UL,
GPIOMUX_FUNC_4 = 4UL,
GPIOMUX_FUNC_5 = 5UL,
GPIOMUX_FUNC_6 = 6UL,
GPIOMUX_FUNC_7 = 7UL,
GPIOMUX_FUNC_8 = 8UL,
GPIOMUX_FUNC_9 = 9UL,
GPIOMUX_FUNC_A = 10UL,
GPIOMUX_FUNC_B = 11UL,
GPIOMUX_FUNC_C = 12UL,
GPIOMUX_FUNC_D = 13UL,
GPIOMUX_FUNC_E = 14UL,
GPIOMUX_FUNC_F = 15UL,
};
enum {
GPIOMUX_PULL_NONE = 0UL << 15,
GPIOMUX_PULL_DOWN = 1UL << 15,
GPIOMUX_PULL_KEEPER = 2UL << 15,
GPIOMUX_PULL_UP = 3UL << 15,
};
#endif
arch/arm/mach-msm/gpiomux-v2.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/io.h>
#include <mach/msm_iomap.h>
#include "gpiomux.h"
void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
{
writel(val & ~GPIOMUX_CTL_MASK,
MSM_TLMM_BASE + 0x1000 + (0x10 * gpio));
}
arch/arm/mach-msm/gpiomux-v2.h 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
#define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
#define GPIOMUX_NGPIOS 173
typedef u16 gpiomux_config_t;
enum {
GPIOMUX_DRV_2MA = 0UL << 6,
GPIOMUX_DRV_4MA = 1UL << 6,
GPIOMUX_DRV_6MA = 2UL << 6,
GPIOMUX_DRV_8MA = 3UL << 6,
GPIOMUX_DRV_10MA = 4UL << 6,
GPIOMUX_DRV_12MA = 5UL << 6,
GPIOMUX_DRV_14MA = 6UL << 6,
GPIOMUX_DRV_16MA = 7UL << 6,
};
enum {
GPIOMUX_FUNC_GPIO = 0UL << 2,
GPIOMUX_FUNC_1 = 1UL << 2,
GPIOMUX_FUNC_2 = 2UL << 2,
GPIOMUX_FUNC_3 = 3UL << 2,
GPIOMUX_FUNC_4 = 4UL << 2,
GPIOMUX_FUNC_5 = 5UL << 2,
GPIOMUX_FUNC_6 = 6UL << 2,
GPIOMUX_FUNC_7 = 7UL << 2,
GPIOMUX_FUNC_8 = 8UL << 2,
GPIOMUX_FUNC_9 = 9UL << 2,
GPIOMUX_FUNC_A = 10UL << 2,
GPIOMUX_FUNC_B = 11UL << 2,
GPIOMUX_FUNC_C = 12UL << 2,
GPIOMUX_FUNC_D = 13UL << 2,
GPIOMUX_FUNC_E = 14UL << 2,
GPIOMUX_FUNC_F = 15UL << 2,
};
enum {
GPIOMUX_PULL_NONE = 0UL,
GPIOMUX_PULL_DOWN = 1UL,
GPIOMUX_PULL_KEEPER = 2UL,
GPIOMUX_PULL_UP = 3UL,
};
#endif
arch/arm/mach-msm/gpiomux.c 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/spinlock.h>
#include "gpiomux.h"
static DEFINE_SPINLOCK(gpiomux_lock);
int msm_gpiomux_write(unsigned gpio,
gpiomux_config_t active,
gpiomux_config_t suspended)
{
struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
unsigned long irq_flags;
gpiomux_config_t setting;
if (gpio >= GPIOMUX_NGPIOS)
return -EINVAL;
spin_lock_irqsave(&gpiomux_lock, irq_flags);
if (active & GPIOMUX_VALID)
cfg->active = active;
if (suspended & GPIOMUX_VALID)
cfg->suspended = suspended;
setting = cfg->ref ? active : suspended;
if (setting & GPIOMUX_VALID)
__msm_gpiomux_write(gpio, setting);
spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
return 0;
}
EXPORT_SYMBOL(msm_gpiomux_write);
int msm_gpiomux_get(unsigned gpio)
{
struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
unsigned long irq_flags;
if (gpio >= GPIOMUX_NGPIOS)
return -EINVAL;
spin_lock_irqsave(&gpiomux_lock, irq_flags);
if (cfg->ref++ == 0 && cfg->active & GPIOMUX_VALID)
__msm_gpiomux_write(gpio, cfg->active);
spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
return 0;
}
EXPORT_SYMBOL(msm_gpiomux_get);
int msm_gpiomux_put(unsigned gpio)
{
struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
unsigned long irq_flags;
if (gpio >= GPIOMUX_NGPIOS)
return -EINVAL;
spin_lock_irqsave(&gpiomux_lock, irq_flags);
BUG_ON(cfg->ref == 0);
if (--cfg->ref == 0 && cfg->suspended & GPIOMUX_VALID)
__msm_gpiomux_write(gpio, cfg->suspended);
spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
return 0;
}
EXPORT_SYMBOL(msm_gpiomux_put);
static int __init gpiomux_init(void)
{
unsigned n;
for (n = 0; n < GPIOMUX_NGPIOS; ++n) {
msm_gpiomux_configs[n].ref = 0;
if (!(msm_gpiomux_configs[n].suspended & GPIOMUX_VALID))
continue;
__msm_gpiomux_write(n, msm_gpiomux_configs[n].suspended);
}
return 0;
}
postcore_initcall(gpiomux_init);
arch/arm/mach-msm/gpiomux.h 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_H
#define __ARCH_ARM_MACH_MSM_GPIOMUX_H
#include <linux/bitops.h>
#include <linux/errno.h>
#if defined(CONFIG_MSM_V2_TLMM)
#include "gpiomux-v2.h"
#else
#include "gpiomux-v1.h"
#endif
/**
* struct msm_gpiomux_config: gpiomux settings for one gpio line.
*
* A complete gpiomux config is the bitwise-or of a drive-strength,
* function, and pull. For functions other than GPIO, the OE
* is hard-wired according to the function. For GPIO mode,
* OE is controlled by gpiolib.
*
* Available settings differ by target; see the gpiomux header
* specific to your target arch for available configurations.
*
* @active: The configuration to be installed when the line is
* active, or its reference count is > 0.
* @suspended: The configuration to be installed when the line
* is suspended, or its reference count is 0.
* @ref: The reference count of the line. For internal use of
* the gpiomux framework only.
*/
struct msm_gpiomux_config {
gpiomux_config_t active;
gpiomux_config_t suspended;
unsigned ref;
};
/**
* @GPIOMUX_VALID: If set, the config field contains 'good data'.
* The absence of this bit will prevent the gpiomux
* system from applying the configuration under all
* circumstances.
*/
enum {
GPIOMUX_VALID = BIT(sizeof(gpiomux_config_t) * BITS_PER_BYTE - 1),
GPIOMUX_CTL_MASK = GPIOMUX_VALID,
};
#ifdef CONFIG_MSM_GPIOMUX
/* Each architecture must provide its own instance of this table.
* To avoid having gpiomux manage any given gpio, one or both of
* the entries can avoid setting GPIOMUX_VALID - the absence
* of that flag will prevent the configuration from being applied
* during state transitions.
*/
extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
/* Increment a gpio's reference count, possibly activating the line. */
int __must_check msm_gpiomux_get(unsigned gpio);
/* Decrement a gpio's reference count, possibly suspending the line. */
int msm_gpiomux_put(unsigned gpio);
/* Install a new configuration to the gpio line. To avoid overwriting
* a configuration, leave the VALID bit out.
*/
int msm_gpiomux_write(unsigned gpio,
gpiomux_config_t active,
gpiomux_config_t suspended);
/* Architecture-internal function for use by the framework only.
* This function can assume the following:
* - the gpio value has passed a bounds-check
* - the gpiomux spinlock has been obtained
*
* This function is not for public consumption. External users
* should use msm_gpiomux_write.
*/
void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val);
#else
static inline int __must_check msm_gpiomux_get(unsigned gpio)
{
return -ENOSYS;
}
static inline int msm_gpiomux_put(unsigned gpio)
{
return -ENOSYS;
}
static inline int msm_gpiomux_write(unsigned gpio,
gpiomux_config_t active,
gpiomux_config_t suspended)
{
return -ENOSYS;
}
#endif
#endif
arch/arm/mach-msm/include/mach/board.h
浏览文件 @ 3c00079b
......@@ -33,6 +33,8 @@ struct msm_acpu_clock_platform_data
struct clk;
extern struct sys_timer msm_timer;
/* common init routines for use by arch/arm/mach-msm/board-*.c */
void __init msm_add_devices(void);
......
arch/arm/mach-msm/include/mach/debug-macro.S
浏览文件 @ 3c00079b
......@@ -19,7 +19,7 @@
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
#ifdef CONFIG_MSM_DEBUG_UART
#ifdef CONFIG_HAS_MSM_DEBUG_UART_PHYS
.macro addruart, rx, tmp
@ see if the MMU is enabled and select appropriate base address
mrc p15, 0, \rx, c1, c0
......
arch/arm/mach-msm/include/mach/dma.h
浏览文件 @ 3c00079b
......@@ -32,10 +32,18 @@ struct msm_dmov_cmd {
void *data;
};
#ifndef CONFIG_ARCH_MSM8X60
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
#else
static inline
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
static inline
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
static inline
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
#endif
#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
......
arch/arm/mach-msm/include/mach/entry-macro-qgic.S 0 → 100644
浏览文件 @ 3c00079b
/*
* Low-level IRQ helper macros
*
* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
#include <asm/hardware/gic.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =gic_cpu_base_addr
ldr \base, [\base]
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
/*
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit:
*
* Migrated the code from ARM MP port to be more consistant
* with interrupt processing , the following still holds true
* however, all interrupts are treated the same regardless of
* if they are local IPI or PPI
*
* Interrupts 0-15 are IPI
* 16-31 are PPI
* (16-18 are the timers)
* 32-1020 are global
* 1021-1022 are reserved
* 1023 is "spurious" (no interrupt)
*
* A simple read from the controller will tell us the number of the
* highest priority enabled interrupt. We then just need to check
* whether it is in the valid range for an IRQ (0-1020 inclusive).
*
* Base ARM code assumes that the local (private) peripheral interrupts
* are not valid, we treat them differently, in that the privates are
* handled like normal shared interrupts with the exception that only
* one processor can register the interrupt and the handler must be
* the same for all processors.
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
9-0 =int # */
bic \irqnr, \irqstat, #0x1c00 @mask src
cmp \irqnr, #15
ldr \tmp, =1021
cmpcc \irqnr, \irqnr
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr
.endm
/* We assume that irqstat (the raw value of the IRQ acknowledge
* register) is preserved from the macro above.
* If there is an IPI, we immediately signal end of interrupt on the
* controller, since this requires the original irqstat value which
* we won't easily be able to recreate later.
*/
.macro test_for_ipi, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #16
strcc \irqstat, [\base, #GIC_CPU_EOI]
cmpcs \irqnr, \irqnr
.endm
/* As above, this assumes that irqstat and base are preserved.. */
.macro test_for_ltirq, irqnr, irqstat, base, tmp
bic \irqnr, \irqstat, #0x1c00
mov \tmp, #0
cmp \irqnr, #16
moveq \tmp, #1
streq \irqstat, [\base, #GIC_CPU_EOI]
cmp \tmp, #0
.endm
arch/arm/mach-msm/include/mach/entry-macro-vic.S 0 → 100644
浏览文件 @ 3c00079b
/*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <mach/msm_iomap.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
@ enable imprecise aborts
cpsie a
mov \base, #MSM_VIC_BASE
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ 0xD0 has irq# or old irq# if the irq has been handled
@ 0xD4 has irq# or -1 if none pending *but* if you just
@ read 0xD4 you never get the first irq for some reason
ldr \irqnr, [\base, #0xD0]
ldr \irqnr, [\base, #0xD4]
cmp \irqnr, #0xffffffff
.endm
arch/arm/mach-msm/include/mach/entry-macro.S
浏览文件 @ 3c00079b
/* arch/arm/mach-msm7200/include/mach/entry-macro.S
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <mach/msm_iomap.h>
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
@ enable imprecise aborts
cpsie a
mov \base, #MSM_VIC_BASE
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@ 0xD0 has irq# or old irq# if the irq has been handled
@ 0xD4 has irq# or -1 if none pending *but* if you just
@ read 0xD4 you never get the first irq for some reason
ldr \irqnr, [\base, #0xD0]
ldr \irqnr, [\base, #0xD4]
cmp \irqnr, #0xffffffff
.endm
#if defined(CONFIG_ARM_GIC)
#include <mach/entry-macro-qgic.S>
#else
#include <mach/entry-macro-vic.S>
#endif
arch/arm/mach-msm/include/mach/gpio.h
浏览文件 @ 3c00079b
......@@ -23,127 +23,4 @@
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/**
* struct msm_gpio - GPIO pin description
* @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
* @label - textual label
*
* Usually, GPIO's are operated by sets.
* This struct accumulate all GPIO information in single source
* and facilitete group operations provided by msm_gpios_xxx()
*/
struct msm_gpio {
u32 gpio_cfg;
const char *label;
};
/**
* msm_gpios_request_enable() - request and enable set of GPIOs
*
* Request and configure set of GPIO's
* In case of error, all operations rolled back.
* Return error code.
*
* @table: GPIO table
* @size: number of entries in @table
*/
int msm_gpios_request_enable(const struct msm_gpio *table, int size);
/**
* msm_gpios_disable_free() - disable and free set of GPIOs
*
* @table: GPIO table
* @size: number of entries in @table
*/
void msm_gpios_disable_free(const struct msm_gpio *table, int size);
/**
* msm_gpios_request() - request set of GPIOs
* In case of error, all operations rolled back.
* Return error code.
*
* @table: GPIO table
* @size: number of entries in @table
*/
int msm_gpios_request(const struct msm_gpio *table, int size);
/**
* msm_gpios_free() - free set of GPIOs
*
* @table: GPIO table
* @size: number of entries in @table
*/
void msm_gpios_free(const struct msm_gpio *table, int size);
/**
* msm_gpios_enable() - enable set of GPIOs
* In case of error, all operations rolled back.
* Return error code.
*
* @table: GPIO table
* @size: number of entries in @table
*/
int msm_gpios_enable(const struct msm_gpio *table, int size);
/**
* msm_gpios_disable() - disable set of GPIOs
*
* @table: GPIO table
* @size: number of entries in @table
*/
void msm_gpios_disable(const struct msm_gpio *table, int size);
/* GPIO TLMM (Top Level Multiplexing) Definitions */
/* GPIO TLMM: Function -- GPIO specific */
/* GPIO TLMM: Direction */
enum {
GPIO_INPUT,
GPIO_OUTPUT,
};
/* GPIO TLMM: Pullup/Pulldown */
enum {
GPIO_NO_PULL,
GPIO_PULL_DOWN,
GPIO_KEEPER,
GPIO_PULL_UP,
};
/* GPIO TLMM: Drive Strength */
enum {
GPIO_2MA,
GPIO_4MA,
GPIO_6MA,
GPIO_8MA,
GPIO_10MA,
GPIO_12MA,
GPIO_14MA,
GPIO_16MA,
};
enum {
GPIO_ENABLE,
GPIO_DISABLE,
};
#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
((((gpio) & 0x3FF) << 4) | \
((func) & 0xf) | \
(((dir) & 0x1) << 14) | \
(((pull) & 0x3) << 15) | \
(((drvstr) & 0xF) << 17))
/**
* extract GPIO pin from bit-field used for gpio_tlmm_config
*/
#define GPIO_PIN(gpio_cfg) (((gpio_cfg) >> 4) & 0x3ff)
#define GPIO_FUNC(gpio_cfg) (((gpio_cfg) >> 0) & 0xf)
#define GPIO_DIR(gpio_cfg) (((gpio_cfg) >> 14) & 0x1)
#define GPIO_PULL(gpio_cfg) (((gpio_cfg) >> 15) & 0x3)
#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf)
int gpio_tlmm_config(unsigned config, unsigned disable);
#endif /* __ASM_ARCH_MSM_GPIO_H */
arch/arm/mach-msm/include/mach/io.h
浏览文件 @ 3c00079b
......@@ -28,6 +28,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
void msm_map_qsd8x50_io(void);
void msm_map_msm7x30_io(void);
void msm_map_msm8x60_io(void);
extern unsigned int msm_shared_ram_phys;
......
arch/arm/mach-msm/include/mach/iommu.h 0 → 100644
浏览文件 @ 3c00079b
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef MSM_IOMMU_H
#define MSM_IOMMU_H
#include <linux/interrupt.h>
/* Maximum number of Machine IDs that we are allowing to be mapped to the same
* context bank. The number of MIDs mapped to the same CB does not affect
* performance, but there is a practical limit on how many distinct MIDs may
* be present. These mappings are typically determined at design time and are
* not expected to change at run time.
*/
#define MAX_NUM_MIDS 16
/**
* struct msm_iommu_dev - a single IOMMU hardware instance
* name Human-readable name given to this IOMMU HW instance
* clk_rate Rate to set for this IOMMU's clock, if applicable to this
* particular IOMMU. 0 means don't set a rate.
* -1 means it is an AXI clock with no valid rate
*
*/
struct msm_iommu_dev {
const char *name;
int clk_rate;
};
/**
* struct msm_iommu_ctx_dev - an IOMMU context bank instance
* name Human-readable name given to this context bank
* num Index of this context bank within the hardware
* mids List of Machine IDs that are to be mapped into this context
* bank, terminated by -1. The MID is a set of signals on the
* AXI bus that identifies the function associated with a specific
* memory request. (See ARM spec).
*/
struct msm_iommu_ctx_dev {
const char *name;
int num;
int mids[MAX_NUM_MIDS];
};
/**
* struct msm_iommu_drvdata - A single IOMMU hardware instance
* @base: IOMMU config port base address (VA)
* @irq: Interrupt number
*
* A msm_iommu_drvdata holds the global driver data about a single piece
* of an IOMMU hardware instance.
*/
struct msm_iommu_drvdata {
void __iomem *base;
int irq;
};
/**
* struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
* @num: Hardware context number of this context
* @pdev: Platform device associated wit this HW instance
* @attached_elm: List element for domains to track which devices are
* attached to them
*
* A msm_iommu_ctx_drvdata holds the driver data for a single context bank
* within each IOMMU hardware instance
*/
struct msm_iommu_ctx_drvdata {
int num;
struct platform_device *pdev;
struct list_head attached_elm;
};
/*
* Look up an IOMMU context device by its context name. NULL if none found.
* Useful for testing and drivers that do not yet fully have IOMMU stuff in
* their platform devices.
*/
struct device *msm_iommu_get_ctx(const char *ctx_name);
/*
* Interrupt handler for the IOMMU context fault interrupt. Hooking the
* interrupt is not supported in the API yet, but this will print an error
* message and dump useful IOMMU registers.
*/
irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
#endif
arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h 0 → 100644
浏览文件 @ 3c00079b
此差异已折叠。
arch/arm/mach-msm/include/mach/irqs-8x60.h 0 → 100644
浏览文件 @ 3c00079b
此差异已折叠。
arch/arm/mach-msm/include/mach/irqs.h
浏览文件 @ 3c00079b
......@@ -24,6 +24,8 @@
#elif defined(CONFIG_ARCH_QSD8X50)
#include "irqs-8x50.h"
#include "sirc.h"
#elif defined(CONFIG_ARCH_MSM8X60)
#include "irqs-8x60.h"
#elif defined(CONFIG_ARCH_MSM_ARM11)
#include "irqs-7x00.h"
#else
......
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h 0 → 100644
浏览文件 @ 3c00079b
此差异已折叠。
arch/arm/mach-msm/include/mach/smp.h 0 → 100644
浏览文件 @ 3c00079b
此差异已折叠。
arch/arm/mach-msm/io.c
浏览文件 @ 3c00079b
此差异已折叠。
arch/arm/mach-msm/iommu.c 0 → 100644
浏览文件 @ 3c00079b
此差异已折叠。
arch/arm/mach-msm/iommu_dev.c 0 → 100644
浏览文件 @ 3c00079b
此差异已折叠。
arch/arm/mach-msm/timer.c
浏览文件 @ 3c00079b
此差异已折叠。
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