diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d940e7bc2d25e26d4457e9f263cba530ad9c6602..817b53d2ce2ed01632f1f25fb9e655ed58c50e33 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -573,7 +573,7 @@ int x86_pmu_hw_config(struct perf_event *event)
 	 * be collected in PEBS on some platforms, e.g. Icelake
 	 */
 	if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
-		if (x86_pmu.pebs_no_xmm_regs)
+		if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
 			return -EINVAL;
 
 		if (!event->attr.precise_ip)
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 767606851492cfd44f7080b49e7a3b45b31eebe9..5c57ea8dce6d1c0a1203418a38f505f4ce1f5abe 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1964,8 +1964,6 @@ void __init intel_ds_init(void)
 	x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
 	x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
 	x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
-	if (x86_pmu.version <= 4)
-		x86_pmu.pebs_no_xmm_regs = 1;
 	if (x86_pmu.pebs) {
 		char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
 		char *pebs_qual = "";
@@ -2021,7 +2019,6 @@ void __init intel_ds_init(void)
 				x86_get_pmu()->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
 			} else {
 				/* Only basic record supported */
-				x86_pmu.pebs_no_xmm_regs = 1;
 				x86_pmu.large_pebs_flags &=
 					~(PERF_SAMPLE_ADDR |
 					  PERF_SAMPLE_TIME |
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index d639627c66de593df9db99382461159467d06933..bfd6f58d3a357951db3099fc61fd5cf3f5f2994d 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -652,8 +652,7 @@ struct x86_pmu {
 			pebs_active		:1,
 			pebs_broken		:1,
 			pebs_prec_dist		:1,
-			pebs_no_tlb		:1,
-			pebs_no_xmm_regs	:1;
+			pebs_no_tlb		:1;
 	int		pebs_record_size;
 	int		pebs_buffer_size;
 	int		max_pebs_events;