Revert "arm64: capabilities: Merge entries for ARM64_WORKAROUND_CLEAN_CACHE"

This reverts commit 8fa0b010.
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

arch/arm64/Kconfig

@@ -322,13 +322,9 @@ menu "Kernel Features"
 
 menu "ARM errata workarounds via the alternatives framework"
 
-config ARM64_WORKAROUND_CLEAN_CACHE
-	def_bool n
-
 config ARM64_ERRATUM_826319
 	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 	default y
-	select ARM64_WORKAROUND_CLEAN_CACHE
 	help
 	  This option adds an alternative code sequence to work around ARM
 	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
@@ -350,7 +346,6 @@ config ARM64_ERRATUM_826319
 config ARM64_ERRATUM_827319
 	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 	default y
-	select ARM64_WORKAROUND_CLEAN_CACHE
 	help
 	  This option adds an alternative code sequence to work around ARM
 	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
@@ -372,7 +367,6 @@ config ARM64_ERRATUM_827319
 config ARM64_ERRATUM_824069
 	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 	default y
-	select ARM64_WORKAROUND_CLEAN_CACHE
 	help
 	  This option adds an alternative code sequence to work around ARM
 	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
@@ -395,7 +389,6 @@ config ARM64_ERRATUM_824069
 config ARM64_ERRATUM_819472
 	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 	default y
-	select ARM64_WORKAROUND_CLEAN_CACHE
 	help
 	  This option adds an alternative code sequence to work around ARM
 	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache

arch/arm64/include/asm/cputype.h

@@ -148,7 +148,6 @@ struct midr_range {
 		.rv_max = MIDR_CPU_VAR_REV(v_max, r_max),	\
 	}
 
-#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
 
 static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,

arch/arm64/kernel/cpu_errata.c

@@ -730,28 +730,24 @@ static const struct midr_range arm64_harden_el2_vectors[] = {
 
 #endif
 
-#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
-static const struct midr_range workaround_clean_cache[] = {
+const struct arm64_cpu_capabilities arm64_errata[] = {
 #if	defined(CONFIG_ARM64_ERRATUM_826319) || \
 	defined(CONFIG_ARM64_ERRATUM_827319) || \
 	defined(CONFIG_ARM64_ERRATUM_824069)
-	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
-	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
-#endif
-#ifdef	CONFIG_ARM64_ERRATUM_819472
-	/* Cortex-A53 r0p[01] : ARM errata 819472 */
-	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
-#endif
-	{},
-};
+	{
+	/* Cortex-A53 r0p[012] */
+		.desc = "ARM errata 826319, 827319, 824069",
+		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
+		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
+		.cpu_enable = cpu_enable_cache_maint_trap,
+	},
 #endif
-
-const struct arm64_cpu_capabilities arm64_errata[] = {
-#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
+#ifdef CONFIG_ARM64_ERRATUM_819472
 	{
-		.desc = "ARM errata 826319, 827319, 824069, 819472",
+	/* Cortex-A53 r0p[01] */
+		.desc = "ARM errata 819472",
 		.capability = ARM64_WORKAROUND_CLEAN_CACHE,
-		ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
+		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
 		.cpu_enable = cpu_enable_cache_maint_trap,
 	},
 #endif