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提交 2f7d10b3 编写于 作者: J Jammy Zhou 提交者： Alex Deucher
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drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2) 

Make the definitions common for all driver components

v2: fix kfd
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
上级 fa9f1d4e
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Showing with 138 addition and 174 deletion
drivers/gpu/drm/amd/amdgpu/amdgpu.h
浏览文件 @ 2f7d10b3
...@@ -47,7 +47,6 @@ ...@@ -47,7 +47,6 @@
#include <drm/amdgpu_drm.h> #include <drm/amdgpu_drm.h>
#include "amd_shared.h" #include "amd_shared.h"
#include "amdgpu_family.h"
#include "amdgpu_mode.h" #include "amdgpu_mode.h"
#include "amdgpu_ih.h" #include "amdgpu_ih.h"
#include "amdgpu_irq.h" #include "amdgpu_irq.h"
...@@ -1900,7 +1899,7 @@ struct amdgpu_device { ...@@ -1900,7 +1899,7 @@ struct amdgpu_device {
struct rw_semaphore exclusive_lock; struct rw_semaphore exclusive_lock;
/* ASIC */ /* ASIC */
enum amdgpu_asic_type asic_type; enum amd_asic_type asic_type;
uint32_t family; uint32_t family;
uint32_t rev_id; uint32_t rev_id;
uint32_t external_rev_id; uint32_t external_rev_id;
......
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
浏览文件 @ 2f7d10b3
...@@ -21,7 +21,7 @@ ...@@ -21,7 +21,7 @@
*/ */
#include "amdgpu_amdkfd.h" #include "amdgpu_amdkfd.h"
#include "amdgpu_family.h" #include "amd_shared.h"
#include <drm/drmP.h> #include <drm/drmP.h>
#include "amdgpu.h" #include "amdgpu.h"
#include <linux/module.h> #include <linux/module.h>
......
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
浏览文件 @ 2f7d10b3
...@@ -897,7 +897,7 @@ bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, ...@@ -897,7 +897,7 @@ bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
if ((id == ASIC_INTERNAL_ENGINE_SS) || if ((id == ASIC_INTERNAL_ENGINE_SS) ||
(id == ASIC_INTERNAL_MEMORY_SS)) (id == ASIC_INTERNAL_MEMORY_SS))
ss->rate /= 100; ss->rate /= 100;
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
return true; return true;
} }
...@@ -1058,7 +1058,7 @@ void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, ...@@ -1058,7 +1058,7 @@ void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
SET_MEMORY_CLOCK_PS_ALLOCATION args; SET_MEMORY_CLOCK_PS_ALLOCATION args;
int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
return; return;
args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
......
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
浏览文件 @ 2f7d10b3
...@@ -48,7 +48,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev) ...@@ -48,7 +48,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
resource_size_t vram_base; resource_size_t vram_base;
resource_size_t size = 256 * 1024; /* ??? */ resource_size_t size = 256 * 1024; /* ??? */
if (!(adev->flags & AMDGPU_IS_APU)) if (!(adev->flags & AMD_IS_APU))
if (!amdgpu_card_posted(adev)) if (!amdgpu_card_posted(adev))
return false; return false;
...@@ -184,7 +184,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) ...@@ -184,7 +184,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
bool found = false; bool found = false;
/* ATRM is for the discrete card only */ /* ATRM is for the discrete card only */
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
return false; return false;
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
...@@ -246,7 +246,7 @@ static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) ...@@ -246,7 +246,7 @@ static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev) static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev)
{ {
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
return igp_read_bios_from_vram(adev); return igp_read_bios_from_vram(adev);
else else
return amdgpu_asic_read_disabled_bios(adev); return amdgpu_asic_read_disabled_bios(adev);
......
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
浏览文件 @ 2f7d10b3
...@@ -63,7 +63,7 @@ bool amdgpu_device_is_px(struct drm_device *dev) ...@@ -63,7 +63,7 @@ bool amdgpu_device_is_px(struct drm_device *dev)
{ {
struct amdgpu_device *adev = dev->dev_private; struct amdgpu_device *adev = dev->dev_private;
if (adev->flags & AMDGPU_IS_PX) if (adev->flags & AMD_IS_PX)
return true; return true;
return false; return false;
} }
...@@ -1377,7 +1377,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, ...@@ -1377,7 +1377,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->ddev = ddev; adev->ddev = ddev;
adev->pdev = pdev; adev->pdev = pdev;
adev->flags = flags; adev->flags = flags;
adev->asic_type = flags & AMDGPU_ASIC_MASK; adev->asic_type = flags & AMD_ASIC_MASK;
adev->is_atom_bios = false; adev->is_atom_bios = false;
adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
adev->mc.gtt_size = 512 * 1024 * 1024; adev->mc.gtt_size = 512 * 1024 * 1024;
......
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
浏览文件 @ 2f7d10b3
...@@ -142,33 +142,33 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); ...@@ -142,33 +142,33 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
static struct pci_device_id pciidlist[] = { static struct pci_device_id pciidlist[] = {
#ifdef CONFIG_DRM_AMDGPU_CIK #ifdef CONFIG_DRM_AMDGPU_CIK
/* Kaveri */ /* Kaveri */
{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
{0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
/* Bonaire */ /* Bonaire */
{0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
{0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
{0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
{0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
{0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
{0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
{0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
...@@ -190,39 +190,39 @@ static struct pci_device_id pciidlist[] = { ...@@ -190,39 +190,39 @@ static struct pci_device_id pciidlist[] = {
{0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
{0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
/* Kabini */ /* Kabini */
{0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
{0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
{0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
{0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
{0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
{0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
{0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
{0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
{0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
/* mullins */ /* mullins */
{0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
#endif #endif
/* topaz */ /* topaz */
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
...@@ -241,11 +241,11 @@ static struct pci_device_id pciidlist[] = { ...@@ -241,11 +241,11 @@ static struct pci_device_id pciidlist[] = {
{0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
{0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
/* carrizo */ /* carrizo */
{0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
{0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
{0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
{0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
{0, 0, 0} {0, 0, 0}
}; };
...@@ -281,7 +281,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, ...@@ -281,7 +281,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
unsigned long flags = ent->driver_data; unsigned long flags = ent->driver_data;
int ret; int ret;
if ((flags & AMDGPU_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
DRM_INFO("This hardware requires experimental hardware support.\n" DRM_INFO("This hardware requires experimental hardware support.\n"
"See modparam exp_hw_support\n"); "See modparam exp_hw_support\n");
return -ENODEV; return -ENODEV;
......
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h
浏览文件 @ 2f7d10b3
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
#include <linux/firmware.h> #include <linux/firmware.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include "amdgpu_family.h" #include "amd_shared.h"
/* General customization: /* General customization:
*/ */
......
drivers/gpu/drm/amd/amdgpu/amdgpu_family.h 已删除 100644 → 0
浏览文件 @ fa9f1d4e
/*
* Copyright 2008 Advanced Micro Devices, Inc.
* Copyright 2008 Red Hat Inc.
* Copyright 2009 Jerome Glisse.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Dave Airlie
* Alex Deucher
* Jerome Glisse
*/
/* this file defines the CHIP_ and family flags used in the pciids,
* its is common between kms and non-kms because duplicating it and
* changing one place is fail.
*/
#ifndef AMDGPU_FAMILY_H
#define AMDGPU_FAMILY_H
/*
* Supported ASIC types
*/
enum amdgpu_asic_type {
CHIP_BONAIRE = 0,
CHIP_KAVERI,
CHIP_KABINI,
CHIP_HAWAII,
CHIP_MULLINS,
CHIP_TOPAZ,
CHIP_TONGA,
CHIP_CARRIZO,
CHIP_LAST,
};
/*
* Chip flags
*/
enum amdgpu_chip_flags {
AMDGPU_ASIC_MASK = 0x0000ffffUL,
AMDGPU_FLAGS_MASK = 0xffff0000UL,
AMDGPU_IS_MOBILITY = 0x00010000UL,
AMDGPU_IS_APU = 0x00020000UL,
AMDGPU_IS_PX = 0x00040000UL,
AMDGPU_EXP_HW_SUPPORT = 0x00080000UL,
};
#endif
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
浏览文件 @ 2f7d10b3
...@@ -96,8 +96,8 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) ...@@ -96,8 +96,8 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
if ((amdgpu_runtime_pm != 0) && if ((amdgpu_runtime_pm != 0) &&
amdgpu_has_atpx() && amdgpu_has_atpx() &&
((flags & AMDGPU_IS_APU) == 0)) ((flags & AMD_IS_APU) == 0))
flags |= AMDGPU_IS_PX; flags |= AMD_IS_PX;
/* amdgpu_device_init should report only fatal error /* amdgpu_device_init should report only fatal error
* like memory allocation failure or iomapping failure, * like memory allocation failure or iomapping failure,
...@@ -451,7 +451,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file ...@@ -451,7 +451,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
dev_info._pad = 0; dev_info._pad = 0;
dev_info.ids_flags = 0; dev_info.ids_flags = 0;
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
......
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
浏览文件 @ 2f7d10b3
...@@ -462,7 +462,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo) ...@@ -462,7 +462,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
int amdgpu_bo_evict_vram(struct amdgpu_device *adev) int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
{ {
/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
if (0 && (adev->flags & AMDGPU_IS_APU)) { if (0 && (adev->flags & AMD_IS_APU)) {
/* Useless to evict on IGP chips */ /* Useless to evict on IGP chips */
return 0; return 0;
} }
......
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
浏览文件 @ 2f7d10b3
...@@ -82,7 +82,7 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev, ...@@ -82,7 +82,7 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev,
mutex_unlock(&adev->pm.mutex); mutex_unlock(&adev->pm.mutex);
/* Can't set dpm state when the card is off */ /* Can't set dpm state when the card is off */
if (!(adev->flags & AMDGPU_IS_PX) || if (!(adev->flags & AMD_IS_PX) ||
(ddev->switch_power_state == DRM_SWITCH_POWER_ON)) (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
amdgpu_pm_compute_clocks(adev); amdgpu_pm_compute_clocks(adev);
fail: fail:
...@@ -538,7 +538,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) ...@@ -538,7 +538,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
/* vce just modifies an existing state so force a change */ /* vce just modifies an existing state so force a change */
if (ps->vce_active != adev->pm.dpm.vce_active) if (ps->vce_active != adev->pm.dpm.vce_active)
goto force; goto force;
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
/* for APUs if the num crtcs changed but state is the same, /* for APUs if the num crtcs changed but state is the same,
* all we need to do is update the display configuration. * all we need to do is update the display configuration.
*/ */
......
drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
浏览文件 @ 2f7d10b3
...@@ -812,7 +812,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a ...@@ -812,7 +812,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
else else
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
if ((adev->flags & AMDGPU_IS_APU) && if ((adev->flags & AMD_IS_APU) &&
(amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
if (is_dp || if (is_dp ||
!amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) { !amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) {
......
drivers/gpu/drm/amd/amdgpu/cik.c
浏览文件 @ 2f7d10b3
...@@ -838,7 +838,7 @@ static u32 cik_get_xclk(struct amdgpu_device *adev) ...@@ -838,7 +838,7 @@ static u32 cik_get_xclk(struct amdgpu_device *adev)
{ {
u32 reference_clock = adev->clock.spll.reference_freq; u32 reference_clock = adev->clock.spll.reference_freq;
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
return reference_clock / 2; return reference_clock / 2;
} else { } else {
...@@ -1235,7 +1235,7 @@ static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) ...@@ -1235,7 +1235,7 @@ static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
if (reset_mask & AMDGPU_RESET_VMC) if (reset_mask & AMDGPU_RESET_VMC)
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK; srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK;
if (!(adev->flags & AMDGPU_IS_APU)) { if (!(adev->flags & AMD_IS_APU)) {
if (reset_mask & AMDGPU_RESET_MC) if (reset_mask & AMDGPU_RESET_MC)
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK; srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK;
} }
...@@ -1411,7 +1411,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) ...@@ -1411,7 +1411,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
dev_warn(adev->dev, "Wait for MC idle timed out !\n"); dev_warn(adev->dev, "Wait for MC idle timed out !\n");
} }
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
kv_save_regs_for_reset(adev, &kv_save); kv_save_regs_for_reset(adev, &kv_save);
/* disable BM */ /* disable BM */
...@@ -1429,7 +1429,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) ...@@ -1429,7 +1429,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
} }
/* does asic init need to be run first??? */ /* does asic init need to be run first??? */
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
kv_restore_regs_for_reset(adev, &kv_save); kv_restore_regs_for_reset(adev, &kv_save);
} }
...@@ -1570,7 +1570,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) ...@@ -1570,7 +1570,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
if (amdgpu_pcie_gen2 == 0) if (amdgpu_pcie_gen2 == 0)
return; return;
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
return; return;
ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
...@@ -1730,7 +1730,7 @@ static void cik_program_aspm(struct amdgpu_device *adev) ...@@ -1730,7 +1730,7 @@ static void cik_program_aspm(struct amdgpu_device *adev)
return; return;
/* XXX double check APUs */ /* XXX double check APUs */
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
return; return;
orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
......
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
浏览文件 @ 2f7d10b3
...@@ -803,11 +803,11 @@ static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, ...@@ -803,11 +803,11 @@ static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
buffer_alloc = 2; buffer_alloc = 2;
} else if (mode->crtc_hdisplay < 4096) { } else if (mode->crtc_hdisplay < 4096) {
mem_cfg = 0; mem_cfg = 0;
buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
} else { } else {
DRM_DEBUG_KMS("Mode too big for LB!\n"); DRM_DEBUG_KMS("Mode too big for LB!\n");
mem_cfg = 0; mem_cfg = 0;
buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
} }
} else { } else {
mem_cfg = 1; mem_cfg = 1;
......
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
浏览文件 @ 2f7d10b3
...@@ -801,11 +801,11 @@ static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, ...@@ -801,11 +801,11 @@ static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
buffer_alloc = 2; buffer_alloc = 2;
} else if (mode->crtc_hdisplay < 4096) { } else if (mode->crtc_hdisplay < 4096) {
mem_cfg = 0; mem_cfg = 0;
buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
} else { } else {
DRM_DEBUG_KMS("Mode too big for LB!\n"); DRM_DEBUG_KMS("Mode too big for LB!\n");
mem_cfg = 0; mem_cfg = 0;
buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
} }
} else { } else {
mem_cfg = 1; mem_cfg = 1;
......
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
浏览文件 @ 2f7d10b3
...@@ -770,11 +770,11 @@ static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev, ...@@ -770,11 +770,11 @@ static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
buffer_alloc = 2; buffer_alloc = 2;
} else if (mode->crtc_hdisplay < 4096) { } else if (mode->crtc_hdisplay < 4096) {
tmp = 0; tmp = 0;
buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
} else { } else {
DRM_DEBUG_KMS("Mode too big for LB!\n"); DRM_DEBUG_KMS("Mode too big for LB!\n");
tmp = 0; tmp = 0;
buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
} }
} else { } else {
tmp = 1; tmp = 1;
......
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
浏览文件 @ 2f7d10b3
...@@ -2173,7 +2173,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) ...@@ -2173,7 +2173,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
adev->gfx.config.mem_max_burst_length_bytes = 256; adev->gfx.config.mem_max_burst_length_bytes = 256;
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
/* Get memory bank mapping mode. */ /* Get memory bank mapping mode. */
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
...@@ -3758,7 +3758,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) ...@@ -3758,7 +3758,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
int r; int r;
/* allocate rlc buffers */ /* allocate rlc buffers */
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
if (adev->asic_type == CHIP_KAVERI) { if (adev->asic_type == CHIP_KAVERI) {
adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
adev->gfx.rlc.reg_list_size = adev->gfx.rlc.reg_list_size =
......
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
浏览文件 @ 2f7d10b3
...@@ -2078,7 +2078,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) ...@@ -2078,7 +2078,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
adev->gfx.config.mem_max_burst_length_bytes = 256; adev->gfx.config.mem_max_burst_length_bytes = 256;
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
/* Get memory bank mapping mode. */ /* Get memory bank mapping mode. */
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
......
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
浏览文件 @ 2f7d10b3
...@@ -636,7 +636,7 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev) ...@@ -636,7 +636,7 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS; adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
/* base offset of vram pages */ /* base offset of vram pages */
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
u64 tmp = RREG32(mmMC_VM_FB_OFFSET); u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
tmp <<= 22; tmp <<= 22;
adev->vm_manager.vram_base_offset = tmp; adev->vm_manager.vram_base_offset = tmp;
...@@ -841,7 +841,7 @@ static int gmc_v7_0_early_init(void *handle) ...@@ -841,7 +841,7 @@ static int gmc_v7_0_early_init(void *handle)
gmc_v7_0_set_gart_funcs(adev); gmc_v7_0_set_gart_funcs(adev);
gmc_v7_0_set_irq_funcs(adev); gmc_v7_0_set_irq_funcs(adev);
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
} else { } else {
u32 tmp = RREG32(mmMC_SEQ_MISC0); u32 tmp = RREG32(mmMC_SEQ_MISC0);
...@@ -957,7 +957,7 @@ static int gmc_v7_0_hw_init(void *handle) ...@@ -957,7 +957,7 @@ static int gmc_v7_0_hw_init(void *handle)
gmc_v7_0_mc_program(adev); gmc_v7_0_mc_program(adev);
if (!(adev->flags & AMDGPU_IS_APU)) { if (!(adev->flags & AMD_IS_APU)) {
r = gmc_v7_0_mc_load_microcode(adev); r = gmc_v7_0_mc_load_microcode(adev);
if (r) { if (r) {
DRM_ERROR("Failed to load MC firmware!\n"); DRM_ERROR("Failed to load MC firmware!\n");
...@@ -1172,7 +1172,7 @@ static int gmc_v7_0_soft_reset(void *handle) ...@@ -1172,7 +1172,7 @@ static int gmc_v7_0_soft_reset(void *handle)
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
if (!(adev->flags & AMDGPU_IS_APU)) if (!(adev->flags & AMD_IS_APU))
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
SRBM_SOFT_RESET, SOFT_RESET_MC, 1); SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
} }
...@@ -1282,7 +1282,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle, ...@@ -1282,7 +1282,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle,
if (state == AMD_CG_STATE_GATE) if (state == AMD_CG_STATE_GATE)
gate = true; gate = true;
if (!(adev->flags & AMDGPU_IS_APU)) { if (!(adev->flags & AMD_IS_APU)) {
gmc_v7_0_enable_mc_mgcg(adev, gate); gmc_v7_0_enable_mc_mgcg(adev, gate);
gmc_v7_0_enable_mc_ls(adev, gate); gmc_v7_0_enable_mc_ls(adev, gate);
} }
......
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
浏览文件 @ 2f7d10b3
...@@ -737,7 +737,7 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev) ...@@ -737,7 +737,7 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS; adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
/* base offset of vram pages */ /* base offset of vram pages */
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
u64 tmp = RREG32(mmMC_VM_FB_OFFSET); u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
tmp <<= 22; tmp <<= 22;
adev->vm_manager.vram_base_offset = tmp; adev->vm_manager.vram_base_offset = tmp;
...@@ -816,7 +816,7 @@ static int gmc_v8_0_early_init(void *handle) ...@@ -816,7 +816,7 @@ static int gmc_v8_0_early_init(void *handle)
gmc_v8_0_set_gart_funcs(adev); gmc_v8_0_set_gart_funcs(adev);
gmc_v8_0_set_irq_funcs(adev); gmc_v8_0_set_irq_funcs(adev);
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
} else { } else {
u32 tmp = RREG32(mmMC_SEQ_MISC0); u32 tmp = RREG32(mmMC_SEQ_MISC0);
...@@ -934,7 +934,7 @@ static int gmc_v8_0_hw_init(void *handle) ...@@ -934,7 +934,7 @@ static int gmc_v8_0_hw_init(void *handle)
gmc_v8_0_mc_program(adev); gmc_v8_0_mc_program(adev);
if (!(adev->flags & AMDGPU_IS_APU)) { if (!(adev->flags & AMD_IS_APU)) {
r = gmc_v8_0_mc_load_microcode(adev); r = gmc_v8_0_mc_load_microcode(adev);
if (r) { if (r) {
DRM_ERROR("Failed to load MC firmware!\n"); DRM_ERROR("Failed to load MC firmware!\n");
...@@ -1147,7 +1147,7 @@ static int gmc_v8_0_soft_reset(void *handle) ...@@ -1147,7 +1147,7 @@ static int gmc_v8_0_soft_reset(void *handle)
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
if (!(adev->flags & AMDGPU_IS_APU)) if (!(adev->flags & AMD_IS_APU))
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
SRBM_SOFT_RESET, SOFT_RESET_MC, 1); SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
} }
......
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
浏览文件 @ 2f7d10b3
...@@ -205,7 +205,7 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) ...@@ -205,7 +205,7 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
u32 tmp; u32 tmp;
unsigned ret; unsigned ret;
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
VCE_HARVEST_FUSE_MACRO__MASK) >> VCE_HARVEST_FUSE_MACRO__MASK) >>
VCE_HARVEST_FUSE_MACRO__SHIFT; VCE_HARVEST_FUSE_MACRO__SHIFT;
......
drivers/gpu/drm/amd/amdgpu/vi.c
浏览文件 @ 2f7d10b3
...@@ -261,7 +261,7 @@ static u32 vi_get_xclk(struct amdgpu_device *adev) ...@@ -261,7 +261,7 @@ static u32 vi_get_xclk(struct amdgpu_device *adev)
u32 reference_clock = adev->clock.spll.reference_freq; u32 reference_clock = adev->clock.spll.reference_freq;
u32 tmp; u32 tmp;
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
return reference_clock; return reference_clock;
tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
...@@ -771,7 +771,7 @@ static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) ...@@ -771,7 +771,7 @@ static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
srbm_soft_reset = srbm_soft_reset =
REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
if (!(adev->flags & AMDGPU_IS_APU)) { if (!(adev->flags & AMD_IS_APU)) {
if (reset_mask & AMDGPU_RESET_MC) if (reset_mask & AMDGPU_RESET_MC)
srbm_soft_reset = srbm_soft_reset =
REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1); REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
...@@ -991,7 +991,7 @@ static void vi_pcie_gen3_enable(struct amdgpu_device *adev) ...@@ -991,7 +991,7 @@ static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
if (amdgpu_pcie_gen2 == 0) if (amdgpu_pcie_gen2 == 0)
return; return;
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
return; return;
ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
...@@ -1019,7 +1019,7 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev, ...@@ -1019,7 +1019,7 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
u32 tmp; u32 tmp;
/* not necessary on CZ */ /* not necessary on CZ */
if (adev->flags & AMDGPU_IS_APU) if (adev->flags & AMD_IS_APU)
return; return;
tmp = RREG32(mmBIF_DOORBELL_APER_EN); tmp = RREG32(mmBIF_DOORBELL_APER_EN);
...@@ -1268,7 +1268,7 @@ static int vi_common_early_init(void *handle) ...@@ -1268,7 +1268,7 @@ static int vi_common_early_init(void *handle)
bool smc_enabled = false; bool smc_enabled = false;
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->flags & AMDGPU_IS_APU) { if (adev->flags & AMD_IS_APU) {
adev->smc_rreg = &cz_smc_rreg; adev->smc_rreg = &cz_smc_rreg;
adev->smc_wreg = &cz_smc_wreg; adev->smc_wreg = &cz_smc_wreg;
} else { } else {
......
drivers/gpu/drm/amd/include/amd_shared.h
浏览文件 @ 2f7d10b3
...@@ -34,6 +34,33 @@ ...@@ -34,6 +34,33 @@
#define AMD_FAMILY_VI 130 /* Iceland, Tonga */ #define AMD_FAMILY_VI 130 /* Iceland, Tonga */
#define AMD_FAMILY_CZ 135 /* Carrizo */ #define AMD_FAMILY_CZ 135 /* Carrizo */
/*
* Supported ASIC types
*/
enum amd_asic_type {
CHIP_BONAIRE = 0,
CHIP_KAVERI,
CHIP_KABINI,
CHIP_HAWAII,
CHIP_MULLINS,
CHIP_TOPAZ,
CHIP_TONGA,
CHIP_CARRIZO,
CHIP_LAST,
};
/*
* Chip flags
*/
enum amd_chip_flags {
AMD_ASIC_MASK = 0x0000ffffUL,
AMD_FLAGS_MASK = 0xffff0000UL,
AMD_IS_MOBILITY = 0x00010000UL,
AMD_IS_APU = 0x00020000UL,
AMD_IS_PX = 0x00040000UL,
AMD_EXP_HW_SUPPORT = 0x00080000UL,
};
enum amd_ip_block_type { enum amd_ip_block_type {
AMD_IP_BLOCK_TYPE_COMMON, AMD_IP_BLOCK_TYPE_COMMON,
AMD_IP_BLOCK_TYPE_GMC, AMD_IP_BLOCK_TYPE_GMC,
......
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