diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h new file mode 100644 index 0000000000000000000000000000000000000000..c87b1ba7590ee00ca2f27060f84d56e9718bb435 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_fw_state.h @@ -0,0 +1,73 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DMUB_FW_STATE_H_ +#define _DMUB_FW_STATE_H_ + +#include "dmub_types.h" + +#pragma pack(push, 1) + +struct dmub_fw_state { + /** + * @phy_initialized_during_fw_boot: + * + * Detects if VBIOS/VBL has ran before firmware boot. + * A value of 1 will usually mean S0i3 boot. + */ + uint8_t phy_initialized_during_fw_boot; + + /** + * @intialized_phy: + * + * Bit vector of initialized PHY. + */ + uint8_t initialized_phy; + + /** + * @enabled_phy: + * + * Bit vector of enabled PHY for DP alt mode switch tracking. + */ + uint8_t enabled_phy; + + /** + * @dmcu_fw_loaded: + * + * DMCU auto load state. + */ + uint8_t dmcu_fw_loaded; + + /** + * @psr_state: + * + * PSR state tracking. + */ + uint8_t psr_state; +}; + +#pragma pack(pop) + +#endif /* _DMUB_FW_STATE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h index fdedbe15e026161d20ce086d3c86f5367b2f5e34..528243e35adda60912d39625f2f24de0fd596f17 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h @@ -67,6 +67,7 @@ #include "dmub_types.h" #include "dmub_cmd.h" #include "dmub_rb.h" +#include "dmub_fw_state.h" #if defined(__cplusplus) extern "C" { @@ -102,7 +103,7 @@ enum dmub_window_id { DMUB_WINDOW_3_VBIOS, DMUB_WINDOW_4_MAILBOX, DMUB_WINDOW_5_TRACEBUFF, - DMUB_WINDOW_6_RESERVED, + DMUB_WINDOW_6_FW_STATE, DMUB_WINDOW_7_RESERVED, DMUB_WINDOW_TOTAL, }; @@ -241,7 +242,8 @@ struct dmub_srv_hw_funcs { const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, - const struct dmub_window *cw5); + const struct dmub_window *cw5, + const struct dmub_window *cw6); void (*setup_mailbox)(struct dmub_srv *dmub, const struct dmub_region *inbox1); @@ -296,11 +298,13 @@ struct dmub_srv_hw_params { * @asic: dmub asic identifier * @user_ctx: user provided context for the dmub_srv * @is_virtual: false if hardware support only + * @fw_state: dmub firmware state pointer */ struct dmub_srv { enum dmub_asic asic; void *user_ctx; bool is_virtual; + volatile const struct dmub_fw_state *fw_state; /* private: internal use only */ struct dmub_srv_base_funcs funcs; diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c index 302dd3d4b77d26a7d5d67314c66cacc84e9bd25a..951ea7053c7e3971bec9ab3702679aac17ab468b 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c @@ -76,7 +76,8 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, - const struct dmub_window *cw5) + const struct dmub_window *cw5, + const struct dmub_window *cw6) { REG_WRITE(DMCUB_REGION3_CW2_OFFSET, cw2->offset.u.low_part); REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, cw2->offset.u.high_part); @@ -106,6 +107,13 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, DMCUB_REGION3_CW5_ENABLE, 1); + + REG_WRITE(DMCUB_REGION3_CW6_OFFSET, cw6->offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, cw6->offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); + REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, + DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, + DMCUB_REGION3_CW6_ENABLE, 1); } void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h index ca7db03b94f72d96de28bf78635215285c33b400..e70a57573467f72445d7c21f0d60f58049a4b288 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h @@ -46,7 +46,8 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, - const struct dmub_window *cw5); + const struct dmub_window *cw5, + const struct dmub_window *cw6); void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1); diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c index b9dc2dd645eb3e7454ea16210211abbad12e784c..9cea7a2d8dbfd36a0b9934818f5a22e6a90a4cbf 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c @@ -78,7 +78,8 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, - const struct dmub_window *cw5) + const struct dmub_window *cw5, + const struct dmub_window *cw6) { union dmub_addr offset; uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset; @@ -118,6 +119,15 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub, REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, DMCUB_REGION3_CW5_ENABLE, 1); + + dmub_dcn21_translate_addr(&cw6->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); + REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, + DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, + DMCUB_REGION3_CW6_ENABLE, 1); } bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h index 9e5f195e288f42cb56b8ccee9675422174513538..f7a93a5dcfa50d505b3089dd6c4f5119dbeda01d 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h @@ -38,7 +38,8 @@ void dmub_dcn21_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, - const struct dmub_window *cw5); + const struct dmub_window *cw5, + const struct dmub_window *cw6); bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub); diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 70c7a4be9ccc0da3a859863a179248e80ea269e0..5f39166d3c08c2e65ae438cd92e4005c5039a834 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -48,13 +48,14 @@ /* Number of windows in use. */ -#define DMUB_NUM_WINDOWS (DMUB_WINDOW_5_TRACEBUFF + 1) +#define DMUB_NUM_WINDOWS (DMUB_WINDOW_6_FW_STATE + 1) /* Base addresses. */ #define DMUB_CW0_BASE (0x60000000) #define DMUB_CW1_BASE (0x61000000) #define DMUB_CW3_BASE (0x63000000) #define DMUB_CW5_BASE (0x65000000) +#define DMUB_CW6_BASE (0x66000000) static inline uint32_t dmub_align(uint32_t val, uint32_t factor) { @@ -158,6 +159,7 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub, struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; + struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; if (!dmub->sw_init) return DMUB_STATUS_INVALID; @@ -184,7 +186,13 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub, trace_buff->base = dmub_align(mail->top, 256); trace_buff->top = trace_buff->base + TRACE_BUF_SIZE; - out->fb_size = dmub_align(trace_buff->top, 4096); + fw_state->base = dmub_align(trace_buff->top, 256); + + /* Align firmware state to size of cache line. */ + fw_state->top = + fw_state->base + dmub_align(sizeof(struct dmub_fw_state), 64); + + out->fb_size = dmub_align(fw_state->top, 4096); return DMUB_STATUS_OK; } @@ -258,9 +266,10 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; + struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; struct dmub_rb_init_params rb_params; - struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5; + struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; struct dmub_region inbox1; if (!dmub->sw_init) @@ -286,7 +295,8 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, if (dmub->hw_funcs.reset) dmub->hw_funcs.reset(dmub); - if (inst_fb && data_fb && bios_fb && mail_fb) { + if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && + fw_state_fb) { cw2.offset.quad_part = data_fb->gpu_addr; cw2.region.base = DMUB_CW0_BASE + inst_fb->size; cw2.region.top = cw2.region.base + data_fb->size; @@ -306,8 +316,15 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, cw5.region.base = DMUB_CW5_BASE; cw5.region.top = cw5.region.base + tracebuff_fb->size; + cw6.offset.quad_part = fw_state_fb->gpu_addr; + cw6.region.base = DMUB_CW6_BASE; + cw6.region.top = cw6.region.base + fw_state_fb->size; + + dmub->fw_state = fw_state_fb->cpu_addr; + if (dmub->hw_funcs.setup_windows) - dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5); + dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, + &cw5, &cw6); if (dmub->hw_funcs.setup_mailbox) dmub->hw_funcs.setup_mailbox(dmub, &inbox1);