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2a32b9b1
编写于
11月 16, 2016
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nouveau/disp/nv50-: specify ctrl/user separately when constructing classes
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
4391d7f5
变更
14
显示空白变更内容
内联
并排
Showing
14 changed file
with
32 addition
and
28 deletion
+32
-28
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
+6
-5
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
+9
-6
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursg84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursg84.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgk104.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgt215.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmg84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmg84.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgk104.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgt215.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c
+3
-3
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
+2
-2
未找到文件。
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c
浏览文件 @
2a32b9b1
...
...
@@ -263,7 +263,7 @@ nv50_disp_chan = {
int
nv50_disp_chan_ctor
(
const
struct
nv50_disp_chan_func
*
func
,
const
struct
nv50_disp_chan_mthd
*
mthd
,
struct
nv50_disp_root
*
root
,
int
c
hid
,
int
head
,
struct
nv50_disp_root
*
root
,
int
c
trl
,
int
user
,
int
head
,
const
struct
nvkm_oclass
*
oclass
,
struct
nv50_disp_chan
*
chan
)
{
...
...
@@ -273,8 +273,8 @@ nv50_disp_chan_ctor(const struct nv50_disp_chan_func *func,
chan
->
func
=
func
;
chan
->
mthd
=
mthd
;
chan
->
root
=
root
;
chan
->
chid
.
ctrl
=
c
hid
;
chan
->
chid
.
user
=
chid
;
chan
->
chid
.
ctrl
=
c
trl
;
chan
->
chid
.
user
=
user
;
chan
->
head
=
head
;
if
(
disp
->
chan
[
chan
->
chid
.
user
])
{
...
...
@@ -288,7 +288,7 @@ nv50_disp_chan_ctor(const struct nv50_disp_chan_func *func,
int
nv50_disp_chan_new_
(
const
struct
nv50_disp_chan_func
*
func
,
const
struct
nv50_disp_chan_mthd
*
mthd
,
struct
nv50_disp_root
*
root
,
int
c
hid
,
int
head
,
struct
nv50_disp_root
*
root
,
int
c
trl
,
int
user
,
int
head
,
const
struct
nvkm_oclass
*
oclass
,
struct
nvkm_object
**
pobject
)
{
...
...
@@ -298,5 +298,6 @@ nv50_disp_chan_new_(const struct nv50_disp_chan_func *func,
return
-
ENOMEM
;
*
pobject
=
&
chan
->
object
;
return
nv50_disp_chan_ctor
(
func
,
mthd
,
root
,
chid
,
head
,
oclass
,
chan
);
return
nv50_disp_chan_ctor
(
func
,
mthd
,
root
,
ctrl
,
user
,
head
,
oclass
,
chan
);
}
drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h
浏览文件 @
2a32b9b1
...
...
@@ -29,11 +29,11 @@ struct nv50_disp_chan_func {
int
nv50_disp_chan_ctor
(
const
struct
nv50_disp_chan_func
*
,
const
struct
nv50_disp_chan_mthd
*
,
struct
nv50_disp_root
*
,
int
c
hid
,
int
head
,
struct
nv50_disp_root
*
,
int
c
trl
,
int
user
,
int
head
,
const
struct
nvkm_oclass
*
,
struct
nv50_disp_chan
*
);
int
nv50_disp_chan_new_
(
const
struct
nv50_disp_chan_func
*
,
const
struct
nv50_disp_chan_mthd
*
,
struct
nv50_disp_root
*
,
int
c
hid
,
int
head
,
struct
nv50_disp_root
*
,
int
c
trl
,
int
user
,
int
head
,
const
struct
nvkm_oclass
*
,
struct
nvkm_object
**
);
extern
const
struct
nv50_disp_chan_func
nv50_disp_pioc_func
;
...
...
@@ -94,13 +94,16 @@ extern const struct nv50_disp_chan_mthd gk104_disp_ovly_chan_mthd;
struct
nv50_disp_pioc_oclass
{
int
(
*
ctor
)(
const
struct
nv50_disp_chan_func
*
,
const
struct
nv50_disp_chan_mthd
*
,
struct
nv50_disp_root
*
,
int
c
hid
,
struct
nv50_disp_root
*
,
int
c
trl
,
int
user
,
const
struct
nvkm_oclass
*
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
);
struct
nvkm_sclass
base
;
const
struct
nv50_disp_chan_func
*
func
;
const
struct
nv50_disp_chan_mthd
*
mthd
;
int
chid
;
struct
{
int
ctrl
;
int
user
;
}
chid
;
};
extern
const
struct
nv50_disp_pioc_oclass
nv50_disp_oimm_oclass
;
...
...
@@ -121,12 +124,12 @@ extern const struct nv50_disp_pioc_oclass gk104_disp_curs_oclass;
int
nv50_disp_curs_new
(
const
struct
nv50_disp_chan_func
*
,
const
struct
nv50_disp_chan_mthd
*
,
struct
nv50_disp_root
*
,
int
c
hid
,
struct
nv50_disp_root
*
,
int
c
trl
,
int
user
,
const
struct
nvkm_oclass
*
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
);
int
nv50_disp_oimm_new
(
const
struct
nv50_disp_chan_func
*
,
const
struct
nv50_disp_chan_mthd
*
,
struct
nv50_disp_root
*
,
int
c
hid
,
struct
nv50_disp_root
*
,
int
c
trl
,
int
user
,
const
struct
nvkm_oclass
*
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursg84.c
浏览文件 @
2a32b9b1
...
...
@@ -33,5 +33,5 @@ g84_disp_curs_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_curs_new
,
.
func
=
&
nv50_disp_pioc_func
,
.
chid
=
7
,
.
chid
=
{
7
,
7
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgf119.c
浏览文件 @
2a32b9b1
...
...
@@ -33,5 +33,5 @@ gf119_disp_curs_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_curs_new
,
.
func
=
&
gf119_disp_pioc_func
,
.
chid
=
13
,
.
chid
=
{
13
,
13
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgk104.c
浏览文件 @
2a32b9b1
...
...
@@ -33,5 +33,5 @@ gk104_disp_curs_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_curs_new
,
.
func
=
&
gf119_disp_pioc_func
,
.
chid
=
13
,
.
chid
=
{
13
,
13
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursgt215.c
浏览文件 @
2a32b9b1
...
...
@@ -33,5 +33,5 @@ gt215_disp_curs_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_curs_new
,
.
func
=
&
nv50_disp_pioc_func
,
.
chid
=
7
,
.
chid
=
{
7
,
7
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/cursnv50.c
浏览文件 @
2a32b9b1
...
...
@@ -33,7 +33,7 @@
int
nv50_disp_curs_new
(
const
struct
nv50_disp_chan_func
*
func
,
const
struct
nv50_disp_chan_mthd
*
mthd
,
struct
nv50_disp_root
*
root
,
int
c
hid
,
struct
nv50_disp_root
*
root
,
int
c
trl
,
int
user
,
const
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
{
...
...
@@ -54,7 +54,7 @@ nv50_disp_curs_new(const struct nv50_disp_chan_func *func,
}
else
return
ret
;
return
nv50_disp_chan_new_
(
func
,
mthd
,
root
,
c
hid
+
head
,
return
nv50_disp_chan_new_
(
func
,
mthd
,
root
,
c
trl
+
head
,
user
+
head
,
head
,
oclass
,
pobject
);
}
...
...
@@ -65,5 +65,5 @@ nv50_disp_curs_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_curs_new
,
.
func
=
&
nv50_disp_pioc_func
,
.
chid
=
7
,
.
chid
=
{
7
,
7
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c
浏览文件 @
2a32b9b1
...
...
@@ -149,7 +149,7 @@ nv50_disp_dmac_new_(const struct nv50_disp_dmac_func *func,
chan
->
func
=
func
;
ret
=
nv50_disp_chan_ctor
(
&
nv50_disp_dmac_func_
,
mthd
,
root
,
chid
,
head
,
oclass
,
&
chan
->
base
);
chid
,
chid
,
head
,
oclass
,
&
chan
->
base
);
if
(
ret
)
return
ret
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmg84.c
浏览文件 @
2a32b9b1
...
...
@@ -33,5 +33,5 @@ g84_disp_oimm_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_oimm_new
,
.
func
=
&
nv50_disp_pioc_func
,
.
chid
=
5
,
.
chid
=
{
5
,
5
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgf119.c
浏览文件 @
2a32b9b1
...
...
@@ -33,5 +33,5 @@ gf119_disp_oimm_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_oimm_new
,
.
func
=
&
gf119_disp_pioc_func
,
.
chid
=
9
,
.
chid
=
{
9
,
9
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgk104.c
浏览文件 @
2a32b9b1
...
...
@@ -33,5 +33,5 @@ gk104_disp_oimm_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_oimm_new
,
.
func
=
&
gf119_disp_pioc_func
,
.
chid
=
9
,
.
chid
=
{
9
,
9
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmgt215.c
浏览文件 @
2a32b9b1
...
...
@@ -33,5 +33,5 @@ gt215_disp_oimm_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_oimm_new
,
.
func
=
&
nv50_disp_pioc_func
,
.
chid
=
5
,
.
chid
=
{
5
,
5
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/oimmnv50.c
浏览文件 @
2a32b9b1
...
...
@@ -33,7 +33,7 @@
int
nv50_disp_oimm_new
(
const
struct
nv50_disp_chan_func
*
func
,
const
struct
nv50_disp_chan_mthd
*
mthd
,
struct
nv50_disp_root
*
root
,
int
c
hid
,
struct
nv50_disp_root
*
root
,
int
c
trl
,
int
user
,
const
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
{
...
...
@@ -54,7 +54,7 @@ nv50_disp_oimm_new(const struct nv50_disp_chan_func *func,
}
else
return
ret
;
return
nv50_disp_chan_new_
(
func
,
mthd
,
root
,
c
hid
+
head
,
return
nv50_disp_chan_new_
(
func
,
mthd
,
root
,
c
trl
+
head
,
user
+
head
,
head
,
oclass
,
pobject
);
}
...
...
@@ -65,5 +65,5 @@ nv50_disp_oimm_oclass = {
.
base
.
maxver
=
0
,
.
ctor
=
nv50_disp_oimm_new
,
.
func
=
&
nv50_disp_pioc_func
,
.
chid
=
5
,
.
chid
=
{
5
,
5
}
,
};
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
浏览文件 @
2a32b9b1
...
...
@@ -250,8 +250,8 @@ nv50_disp_root_pioc_new_(const struct nvkm_oclass *oclass,
{
const
struct
nv50_disp_pioc_oclass
*
sclass
=
oclass
->
priv
;
struct
nv50_disp_root
*
root
=
nv50_disp_root
(
oclass
->
parent
);
return
sclass
->
ctor
(
sclass
->
func
,
sclass
->
mthd
,
root
,
sclass
->
chid
,
oclass
,
data
,
size
,
pobject
);
return
sclass
->
ctor
(
sclass
->
func
,
sclass
->
mthd
,
root
,
sclass
->
chid
.
ctrl
,
sclass
->
chid
.
user
,
oclass
,
data
,
size
,
pobject
);
}
static
int
...
...
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