diff --git a/tools/perf/pmu-events/arch/powerpc/power9/frontend.json b/tools/perf/pmu-events/arch/powerpc/power9/frontend.json index 7e62c46d7a2008ae31b725886f09c122a923e9e5..c63a919eda981bbc972e08d55a03a35ab4208645 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/frontend.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/frontend.json @@ -79,11 +79,6 @@ "EventName": "PM_LD_MISS_L1", "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load." }, - {, - "EventCode": "0x400F0", - "EventName": "PM_LD_MISS_L1", - "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load." - }, {, "EventCode": "0x2E01A", "EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT", @@ -374,4 +369,4 @@ "EventName": "PM_IPTEG_FROM_L31_ECO_MOD", "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/powerpc/power9/other.json b/tools/perf/pmu-events/arch/powerpc/power9/other.json index 00f3d2a21f3192e1dde8b9e80f174338a52b4174..54cc3be00fc2d84903ce127eb9554ec7054dd9ed 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/other.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/other.json @@ -604,11 +604,6 @@ "EventName": "PM_L2_RTY_LD", "BriefDescription": "RC retries on PB for any load from core (excludes DCBFs)" }, - {, - "EventCode": "0x3689E", - "EventName": "PM_L2_RTY_LD", - "BriefDescription": "RC retries on PB for any load from core (excludes DCBFs)" - }, {, "EventCode": "0xE08C", "EventName": "PM_LSU0_ERAT_HIT", @@ -714,11 +709,6 @@ "EventName": "PM_L3_RD0_BUSY", "BriefDescription": "Lifetime, sample of RD machine 0 valid" }, - {, - "EventCode": "0x468B4", - "EventName": "PM_L3_RD0_BUSY", - "BriefDescription": "Lifetime, sample of RD machine 0 valid" - }, {, "EventCode": "0x46080", "EventName": "PM_L2_DISP_ALL_L2MISS", @@ -849,21 +839,11 @@ "EventName": "PM_RC0_BUSY", "BriefDescription": "RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)" }, - {, - "EventCode": "0x2608C", - "EventName": "PM_RC0_BUSY", - "BriefDescription": "RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)" - }, {, "EventCode": "0x36082", "EventName": "PM_L2_LD_DISP", "BriefDescription": "All successful I-or-D side load dispatches for this thread (excludes i_l2mru_tch_reqs)." }, - {, - "EventCode": "0x1609E", - "EventName": "PM_L2_LD_DISP", - "BriefDescription": "All successful D side load dispatches for this thread (L2 miss + L2 hits)" - }, {, "EventCode": "0xF8B0", "EventName": "PM_L3_SW_PREF", @@ -1039,11 +1019,6 @@ "EventName": "PM_L3_CO_MEPF", "BriefDescription": "L3 castouts in Mepf state for this thread" }, - {, - "EventCode": "0x168A0", - "EventName": "PM_L3_CO_MEPF", - "BriefDescription": "L3 CO of line in Mep state (includes casthrough to memory). The Mepf state indicates that a line was brought in to satisfy an L3 prefetch request" - }, {, "EventCode": "0x460A2", "EventName": "PM_L3_LAT_CI_HIT", @@ -1149,11 +1124,6 @@ "EventName": "PM_L2_RTY_ST", "BriefDescription": "RC retries on PB for any store from core (excludes DCBFs)" }, - {, - "EventCode": "0x4689E", - "EventName": "PM_L2_RTY_ST", - "BriefDescription": "RC retries on PB for any store from core (excludes DCBFs)" - }, {, "EventCode": "0x24040", "EventName": "PM_INST_FROM_L2_MEPF", @@ -1254,11 +1224,6 @@ "EventName": "PM_CO0_BUSY", "BriefDescription": "CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point)" }, - {, - "EventCode": "0x4608C", - "EventName": "PM_CO0_BUSY", - "BriefDescription": "CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point)" - }, {, "EventCode": "0x2C122", "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC", @@ -1394,11 +1359,6 @@ "EventName": "PM_IPTEG_FROM_LMEM", "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request" }, - {, - "EventCode": "0x40006", - "EventName": "PM_ISLB_MISS", - "BriefDescription": "Number of ISLB misses for this thread" - }, {, "EventCode": "0xD8A8", "EventName": "PM_ISLB_MISS", @@ -1514,11 +1474,6 @@ "EventName": "PM_L2_INST", "BriefDescription": "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)." }, - {, - "EventCode": "0x3609E", - "EventName": "PM_L2_INST", - "BriefDescription": "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)" - }, {, "EventCode": "0x3504C", "EventName": "PM_IPTEG_FROM_DL4", @@ -1689,11 +1644,6 @@ "EventName": "PM_L2_LD_HIT", "BriefDescription": "All successful I-or-D side load dispatches for this thread that were L2 hits (excludes i_l2mru_tch_reqs)" }, - {, - "EventCode": "0x2609E", - "EventName": "PM_L2_LD_HIT", - "BriefDescription": "All successful D side load dispatches for this thread that were L2 hits for this thread" - }, {, "EventCode": "0x168AC", "EventName": "PM_L3_CI_USAGE", @@ -1794,21 +1744,11 @@ "EventName": "PM_L3_WI0_BUSY", "BriefDescription": "Rotating sample of 8 WI valid" }, - {, - "EventCode": "0x260B6", - "EventName": "PM_L3_WI0_BUSY", - "BriefDescription": "Rotating sample of 8 WI valid (duplicate)" - }, {, "EventCode": "0x368AC", "EventName": "PM_L3_CO0_BUSY", "BriefDescription": "Lifetime, sample of CO machine 0 valid" }, - {, - "EventCode": "0x468AC", - "EventName": "PM_L3_CO0_BUSY", - "BriefDescription": "Lifetime, sample of CO machine 0 valid" - }, {, "EventCode": "0x2E040", "EventName": "PM_DPTEG_FROM_L2_MEPF", @@ -1839,11 +1779,6 @@ "EventName": "PM_L3_P0_PF_RTY", "BriefDescription": "L3 PF received retry port 0, every retry counted" }, - {, - "EventCode": "0x260AE", - "EventName": "PM_L3_P0_PF_RTY", - "BriefDescription": "L3 PF received retry port 0, every retry counted" - }, {, "EventCode": "0x268B2", "EventName": "PM_L3_LOC_GUESS_WRONG", @@ -1894,11 +1829,6 @@ "EventName": "PM_L3_SN0_BUSY", "BriefDescription": "Lifetime, sample of snooper machine 0 valid" }, - {, - "EventCode": "0x460AC", - "EventName": "PM_L3_SN0_BUSY", - "BriefDescription": "Lifetime, sample of snooper machine 0 valid" - }, {, "EventCode": "0x3005C", "EventName": "PM_BFU_BUSY", @@ -1934,11 +1864,6 @@ "EventName": "PM_L3_PF0_BUSY", "BriefDescription": "Lifetime, sample of PF machine 0 valid" }, - {, - "EventCode": "0x460B4", - "EventName": "PM_L3_PF0_BUSY", - "BriefDescription": "Lifetime, sample of PF machine 0 valid" - }, {, "EventCode": "0xC0B0", "EventName": "PM_LSU_FLUSH_UE", @@ -2084,11 +2009,6 @@ "EventName": "PM_L3_P1_CO_RTY", "BriefDescription": "L3 CO received retry port 1 (memory only), every retry counted" }, - {, - "EventCode": "0x468AE", - "EventName": "PM_L3_P1_CO_RTY", - "BriefDescription": "L3 CO received retry port 3 (memory only), every retry counted" - }, {, "EventCode": "0xC0AC", "EventName": "PM_LSU_FLUSH_EMSH", @@ -2194,11 +2114,6 @@ "EventName": "PM_L2_SN_M_WR_DONE", "BriefDescription": "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)" }, - {, - "EventCode": "0x46886", - "EventName": "PM_L2_SN_M_WR_DONE", - "BriefDescription": "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)" - }, {, "EventCode": "0x489C", "EventName": "PM_BR_CORECT_PRED_TAKEN_CMPL", @@ -2289,21 +2204,11 @@ "EventName": "PM_SN0_BUSY", "BriefDescription": "SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point)" }, - {, - "EventCode": "0x26090", - "EventName": "PM_SN0_BUSY", - "BriefDescription": "SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point)" - }, {, "EventCode": "0x360AE", "EventName": "PM_L3_P0_CO_RTY", "BriefDescription": "L3 CO received retry port 0 (memory only), every retry counted" }, - {, - "EventCode": "0x460AE", - "EventName": "PM_L3_P0_CO_RTY", - "BriefDescription": "L3 CO received retry port 0 (memory only), every retry counted" - }, {, "EventCode": "0x168A8", "EventName": "PM_L3_WI_USAGE", @@ -2339,26 +2244,11 @@ "EventName": "PM_L3_P1_PF_RTY", "BriefDescription": "L3 PF received retry port 1, every retry counted" }, - {, - "EventCode": "0x268AE", - "EventName": "PM_L3_P1_PF_RTY", - "BriefDescription": "L3 PF received retry port 3, every retry counted" - }, {, "EventCode": "0x46082", "EventName": "PM_L2_ST_DISP", "BriefDescription": "All successful D-side store dispatches for this thread " }, - {, - "EventCode": "0x1689E", - "EventName": "PM_L2_ST_DISP", - "BriefDescription": "All successful D-side store dispatches for this thread (L2 miss + L2 hits)" - }, - {, - "EventCode": "0x36880", - "EventName": "PM_L2_INST_MISS", - "BriefDescription": "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)" - }, {, "EventCode": "0x4609E", "EventName": "PM_L2_INST_MISS", @@ -2429,11 +2319,6 @@ "EventName": "PM_INST_DISP", "BriefDescription": "# PPC Dispatched" }, - {, - "EventCode": "0x300F2", - "EventName": "PM_INST_DISP", - "BriefDescription": "# PPC Dispatched" - }, {, "EventCode": "0x4E05E", "EventName": "PM_TM_OUTER_TBEGIN_DISP", @@ -2459,11 +2344,6 @@ "EventName": "PM_L2_ST_HIT", "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits" }, - {, - "EventCode": "0x2689E", - "EventName": "PM_L2_ST_HIT", - "BriefDescription": "All successful D-side store dispatches that were L2 hits for this thread" - }, {, "EventCode": "0x360A8", "EventName": "PM_L3_CO", diff --git a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json index 47a82568a8df9f1330c2ed8ce39ffb531fcc874f..bc2db636dabf1612c7c698fb3555319f763755c7 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json @@ -419,11 +419,6 @@ "EventName": "PM_INST_GRP_PUMP_MPRED_RTY", "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch" }, - {, - "EventCode": "0x10016", - "EventName": "PM_DSLB_MISS", - "BriefDescription": "Data SLB Miss - Total of all segment sizes" - }, {, "EventCode": "0xD0A8", "EventName": "PM_DSLB_MISS", @@ -554,4 +549,4 @@ "EventName": "PM_MRK_DATA_FROM_L21_SHR_CYC", "BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load" } -] \ No newline at end of file +] diff --git a/tools/perf/pmu-events/arch/powerpc/power9/pmc.json b/tools/perf/pmu-events/arch/powerpc/power9/pmc.json index a2c95a99e16899af461afad94ea425bb19b81305..3ef8a10aac8638965391ffef28052f5f2bc59ac5 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/pmc.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/pmc.json @@ -4,11 +4,6 @@ "EventName": "PM_BR_2PATH", "BriefDescription": "Branches that are not strongly biased" }, - {, - "EventCode": "0x40036", - "EventName": "PM_BR_2PATH", - "BriefDescription": "Branches that are not strongly biased" - }, {, "EventCode": "0x40056", "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH", @@ -124,4 +119,4 @@ "EventName": "PM_1FLOP_CMPL", "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed" } -] \ No newline at end of file +]