LoongArch: Change definition of cpu_relax() for Loongson-3

LoongArch inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I6BWFP

--------------------------------

This patch changes the definition of cpu_relax() to smp_mb() for
Loongson-3, forcing a flush of the SFB on SMP systems which will cause
any pending writes to make it as far as the L1 caches where they will
become visible to other CPUs. If the kernel is not compiled for SMP
support, this will expand to a barrier() as before.

Reference
commit a3071886 ("MIPS: Change definition of cpu_relax() for Loongson-3")
for detail.
Signed-off-by: NHuacai Chen <chenhuacai@loongson.cn>
Signed-off-by: NHongchen Zhang <zhanghongchen@loongson.cn>
Change-Id: I1ad7efc19b77ead5932ff8429819db0856fb8e33
(cherry picked from commit 923ddb84)

arch/loongarch/include/asm/vdso/processor.h

@@ -7,7 +7,16 @@
 
 #ifndef __ASSEMBLY__
 
-#define cpu_relax()	barrier()
+/*
+ * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
+ * tight read loop is executed, because reads take priority over writes & the
+ * hardware (incorrectly) doesn't ensure that writes will eventually occur.
+ *
+ * Since spin loops of any kind should have a cpu_relax() in them, force an SFB
+ * flush from cpu_relax() such that any pending writes will become visible as
+ * expected.
+ */
+#define cpu_relax()	smp_mb()
 
 #endif /* __ASSEMBLY__ */